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d a t a sh eet product speci?cation 2004 mar 04 integrated circuits SAA7104E; saa7105e digital video encoder
2004 mar 04 2 philips semiconductors product speci?cation digital video encoder SAA7104E; saa7105e contents 1 features 2 general description 3 quick reference data 4 ordering information 5 block diagram 6 pinning 7 functional description 7.1 reset conditions 7.2 input formatter 7.3 rgb lut 7.4 cursor insertion 7.5 rgb y-c b -c r matrix 7.6 horizontal scaler 7.7 vertical scaler and anti-flicker filter 7.8 fifo 7.9 border generator 7.10 oscillator and discrete time oscillator (dto) 7.11 low-pass clock generation circuit (cgc) 7.12 encoder 7.13 rgb processor 7.14 triple dac 7.15 hd data path 7.16 timing generator 7.17 pattern generator for hd sync pulses 7.18 i 2 c-bus interface 7.19 power-down modes 7.20 programming the SAA7104E; saa7105e 7.21 input levels and formats 7.22 bit allocation map 7.23 i 2 c-bus format 7.24 slave receiver 7.25 slave transmitter 8 boundary scan test 8.1 initialization of boundary scan circuit 8.2 device identification codes 9 limiting values 10 thermal characteristics 11 characteristics 11.1 teletext timing 12 application information 12.1 reconstruction filter 12.2 analog output voltages 12.3 suggestions for a board layout 13 package outline 14 soldering 14.1 introduction to soldering surface mount packages 14.2 reflow soldering 14.3 wave soldering 14.4 manual soldering 14.5 suitability of surface mount ic packages for wave and reflow soldering methods 15 data sheet status 16 definitions 17 disclaimers 18 purchase of philips i 2 c components
2004 mar 04 3 philips semiconductors product speci?cation digital video encoder SAA7104E; saa7105e 1 features digital pal/ntsc encoder with integrated high quality scaler and anti-flicker filter for tv output from a pc supports intel a digital video out (dvo) low voltage interfacing to graphics controller 27 mhz crystal-stable subcarrier generation maximum graphics pixel clock 85 mhz at double edged clocking, synthesized on-chip or from external source programmable assignment of clock edge to bytes (in double edged mode) synthesizable pixel clock (pixclk) with minimized output jitter, can be used as reference clock for the vgc, as well) pixclk output and bi-phase pixclk input (vgc clock loop-through possible) hot-plug detection through dedicated interrupt pin supported vga resolutions for pal or ntsc legacy video output up to 1280 1024 graphics data at 60 or 50 hz frame rate supported vga resolutions for hdtv output up to 1920 1080 interlaced graphics data at 60 or 50 hz frame rate three digital-to-analog converters (dacs) for cvbs (blue, c b ), vbs (green, cvbs) and c (red, c r )at 27 mhz sample rate (signals in parenthesis are optionally), all at 10-bit resolution non-interlaced c b -y-c r or rgb input at maximum 4:4:4 sampling downscaling and upscaling from 50 to 400% optional interlaced c b -y-c r input of digital versatile disk (dvd) signals optional non-interlaced rgb output to drive second vga monitor (bypass mode, maximum 85 mhz) 3 256 bytes rgb look-up table (lut) support for hardware cursor hdtv up to 1920 1080 interlaced and 1280 720 progressive, including 3-level sync pulses programmable border colour of underscan area programmable 5 line anti-flicker filter on-chip 27 mhz crystal oscillator (3rd-harmonic or fundamental 27 mhz crystal) fast i 2 c-bus control port (400 khz) encoder can be master or slave adjustable output levels for the dacs programmable horizontal and vertical input synchronization phase programmable horizontal sync output phase internal colour bar generator (cbg) optional support of various vertical blanking interval (vbi) data insertion macrovision ? (1) pay-per-view copy protection system rev. 7.01, rev. 6.1 and rev. 1.03 (525p) as option; this applies to the SAA7104E only. the device is protected by usa patent numbers 4631603, 4577216 and 4819098 and other intellectual property rights. use of the macrovision anti-copy process in the device is licensed for non-commercial home use only. reverse engineering or disassembly is prohibited. please contact your nearest philips semiconductors sales office for more information. optional cross-colour reduction for pal and ntsc cvbs outputs power-save modes joint test action group (jtag) boundary scan test monolithic cmos 3.3 v device, 5 v tolerant i/os. (1) macrovision ? is a trademark of the macrovision corporation.
2004 mar 04 4 philips semiconductors product speci?cation digital video encoder SAA7104E; saa7105e 2 general description the SAA7104E; saa7105e is an advanced next-generation video encoder which converts pc graphics data at maximum 1280 1024 resolution (optionally 1920 1080 interlaced) to pal (50 hz) or ntsc (60 hz) video signals. a programmable scaler and anti-flicker filter (maximum 5 lines) ensures properly sized and flicker-free tv display as cvbs or s-video output. alternatively, the three digital-to-analog converters (dacs) can output rgb signals together with a ttl composite sync to feed scart connectors. when the scaler/interlacer is bypassed, a second vga monitor can be connected to the rgb outputs and separate h and v-syncs as well, thereby serving as an auxiliary monitor at maximum 1280 1024 resolution/60 hz (pixclk < 85 mhz). alternatively this port can provide y, p b and p r signals for hdtv monitors. the device includes a sync/clock generator and on-chip dacs. all inputs intended to interface to the host graphics controller are designed for low-voltage signals between down to 1.1 v and up to 3.6 v. 3 quick reference data 4 ordering information symbol parameter min. typ. max. unit v dda analog supply voltage 3.15 3.3 3.45 v v ddd digital supply voltage 3.15 3.3 3.45 v i dda analog supply current 1 110 115 ma i ddd digital supply current 1 175 200 ma v i input signal voltage levels ttl compatible v o(p-p) analog cvbs output signal voltage for a 100/100 colour bar at 75/2 w load (peak-to-peak value) - 1.23 - v r l load resistance - 37.5 -w ile lf(dac) low frequency integral linearity error of dacs -- 3 lsb dle lf(dac) low frequency differential linearity error of dacs -- 1 lsb t amb ambient temperature 0 - 70 c type number package name description version SAA7104E bga156 plastic ball grid array package; 156 balls; body 15 15 1.15 mm sot472-1 saa7105e
2004 mar 04 5 philips semiconductors product speci?cation digital video encoder SAA7104E; saa7105e 2004 mar 04 5 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 5 block diagram vertical scaler vertical filter horizontal scaler decimator 4 : 4 : 4 to 4 : 2 : 2 triple dac blue_cb_cvbs trst dump rset tdi tdo tms tck green_vbs_cvbs red_cr_c_cvbs c6 c7 c8 vsm d7 hsm_csync d8 tvd f12 border generator fifo lut + cursor rgb to y-c b -c r matrix fifo + upsampling video encoder hd output i 2 c-bus control crystal oscillator timing generator g1 a6 a5 c3 fsvgc vsvgc xtalo 27 mhz ttx_sres xtali hsvgc cbo ttxrq_xclko2 f1 g3 g2 sda scl e2 d2 e3 c4 pixel clock synthesizer input formatter v dda1 c1, c2, b1, b2, a2, b4, b3, a3, f3, h1, h2, h3 a10, b9, c9, d9 v dda2 b6 v dda3 d6 v dda4 b6 v ssa1 b8 v ssa2 a8 v ddd1 f4 v ddd2 d4 v ddd3 d4 a4 a7, b7 a9 b5 d1 d3 e1 v ddd4 d4 v ssd1 c5, d5, e4 v ssd2 c5, d5, e4 v ssd3 c5, d5, e4 v ssd4 c5, d5, e4 f2 pd11 to pd0 pixclki g4 pixclko mhc572 SAA7104E saa7105e reset fig.1 block diagram.
2004 mar 04 6 philips semiconductors product speci?cation digital video encoder SAA7104E; saa7105e 6 pinning symbol pin type (1) description pd7 a2 i msb with c b -y-c r 4 : 2 : 2; see tables 9 to 14 for pin assignment pd4 a3 i msb - 3 with c b -y-c r 4 : 2 : 2; see tables 9 to 14 for pin assignment trst a4 i/pu test reset input for bst; active low; notes 2, 3 and 4 xtali a5 i crystal oscillator input xtalo a6 o crystal oscillator output dump a7, b7 o dac reference pin; connected via 12 w resistor to analog ground v ssa2 a8 s analog ground 2 rset a9 o dac reference pin; connected via 1 k w resistor to analog ground (do not use capacitor in parallel with 1 k w resistor) v dda1 a10, b9, c9, d9 s analog supply voltage 1 (3.3 v for dacs) pd9 b1 i see tables 9 to 14 for pin assignment pd8 b2 i see tables 9 to 14 for pin assignment pd5 b3 i msb - 2 with c b -y-c r 4 : 2 : 2; see tables 9 to 14 for pin assignment pd6 b4 i msb - 1 with c b -y-c r 4 : 2 : 2; see tables 9 to 14 for pin assignment tdi b5 i test data input for bst; note 2 v dda2 b6 s analog supply voltage 2 (3.3 v for dacs) v dda4 b6 s analog supply voltage 4 (3.3 v) v ssa1 b8 s analog ground 1 pd11 c1 i see tables 9 to 14 for pin assignment pd10 c2 i see tables 9 to 14 for pin assignment ttx_sres c3 i teletext input or sync reset input ttxrq_xclko2 c4 o teletext request output or 13.5 mhz clock output of the crystal oscillator; note 5 v ssd1 c5, d5, e4 s digital ground 1 v ssd2 c5, d5, e4 s digital ground 2 v ssd3 c5, d5, e4 s digital ground 3 v ssd4 c5, d5, e4 s digital ground 4 blue_cb_cvbs c6 o analog output of blue or c b or cvbs signal green_vbs_cvbs c7 o analog output of green or vbs or cvbs signal red_cr_c_cvbs c8 o analog output of red or c r or c or cvbs signal tdo d1 o test data output for bst; note 2 reset d2 i reset input; active low tms d3 i/pu test mode select input for boundary scan test (bst); note 2 v ddd2 d4 s digital supply voltage 2 (3.3 v for i/os) v ddd3 d4 s digital supply voltage 3 (3.3 v for core) v ddd4 d4 s digital supply voltage 4 (3.3 v for core) v dda3 d6 s analog supply voltage 3 (3.3 v for oscillator)
2004 mar 04 7 philips semiconductors product speci?cation digital video encoder SAA7104E; saa7105e notes 1. pin type: i = input, o = output, s = supply, pu = pull-up. 2. in accordance with the ieee1149.1 standard the pins tdi, tms, tck and trst are input pins with an internal pull-up resistor and tdo is a 3-state output pin. 3. for board design without boundary scan implementation connect trst to ground. 4. this pin provides easy initialization of the boundary scan test (bst) circuit. trst can be used to force the test access port (tap) controller to the test_logic_reset state (normal operation) at once. 5. the pins fsvgc, vsvgc, cbo, hsvgc and ttxrq_xclko2 are used for bootstrapping; see section 7.1. vsm d7 o vertical synchronization output to monitor (non-interlaced auxiliary rgb) hsm_csync d8 o horizontal synchronization output to monitor (non-interlaced auxiliary rgb) or composite sync for rgb-scart tck e1 i/pu test clock input for bst; note 2 scl e2 i i 2 c-bus serial clock input hsvgc e3 i/o horizontal synchronization output to vgc (optional input); note 5 reserved e12 - to be reserved for future applications vsvgc f1 i/o vertical synchronization output to vgc (optional input); note 5 pixclki f2 i pixel clock input (looped through) pd3 f3 i msb - 4 with c b -y-c r 4 : 2 : 2; see tables 9 to 14 for pin assignment v ddd1 f4 s digital supply voltage 1 for pins pd11 to pd0, pixclki, pixclko, fsvgc, vsvgc, hsvgc, cbo and tvd tvd f12 o interrupt if tv is detected at dac output fsvgc g1 i/o frame synchronization output to video graphics controller (vgc) (optional input); note 5 sda g2 i/o i 2 c-bus serial data input/output cbo g3 i/o composite blanking output to vgc; active low; note 5 pixclko g4 o pixel clock output to vgc pd2 h1 i msb - 5 with c b -y-c r 4 : 2 : 2; see tables 9 to 14 for pin assignment pd1 h2 i msb - 6 with c b -y-c r 4 : 2 : 2; see tables 9 to 14 for pin assignment pd0 h3 i msb - 7 with c b -y-c r 4 : 2 : 2; see tables 9 to 14 for pin assignment symbol pin type (1) description
2004 mar 04 8 philips semiconductors product speci?cation digital video encoder SAA7104E; saa7105e table 1 pin assignment (top view) 1 2 3 4 5 6 7 8 91011121314 a pd7 pd4 trst xtali xtalo dump v ssa2 rset v dda1 b pd9 pd8 pd5 pd6 tdi v dda2 v dda4 dump v ssa1 v dda1 c pd11 pd10 ttx_ sres ttxrq_ xclko2 v ssd1 v ssd2 v ssd3 v ssd4 blue_ cb_ cvbs green_ vbs_ cvbs red_ cr_ c_ cvbs v dda1 d tdo reset tms v ddd2 v ddd3 v ddd4 v ssd1 v ssd2 v ssd3 v ssd4 v dda3 vsm hsm_ csync v dda1 e tck scl hsvgc v ssd1 v ssd2 v ssd3 v ssd4 reserved f vsvgcpixclki pd3 v ddd1 tvd g fsvgc sda cbo pixclko h pd2 pd1 pd0 j k l m n p
2004 mar 04 9 philips semiconductors product speci?cation digital video encoder SAA7104E; saa7105e handbook, halfpage 1 a b c d e f g h j k l m n p 2 3 4 5 6 7 8 9 10 11 12 13 14 mhc566 SAA7104E saa7105e fig.2 pin configuration. 7 functional description the digital video encoder encodes digital luminance and colour difference signals (c b -y-c r ) or digital rgb signals into analog cvbs, s-video and, optionally, rgb or c r -y-c b signals. ntsc m, pal b/g and sub-standards are supported. the SAA7104E; saa7105e can be directly connected to a pc video graphics controller with a maximum resolution of 1280 1024 (progressive) or 1920 1080 (interlaced) at a 50 or 60 hz frame rate. a programmable scaler scales the computer graphics picture so that it will fit into a standard tv screen with an adjustable underscan area. non-interlaced-to-interlaced conversion is optimized with an adjustable anti-flicker filter for a flicker-free display at a very high sharpness. besides the most common 16-bit 4 :2:2 c b -y-c r input format (using 8 pins with double edge clocking), other c b -y-c r and rgb formats are also supported; see tables 9 to 14. a complete 3 256 bytes look-up table (lut), which can be used, for example, as a separate gamma corrector, is located in the rgb domain; it can be loaded either through the video input port pd (pixel data) or via the i 2 c-bus. the SAA7104E; saa7105e supports a 32 32 2-bit hardware cursor, the pattern of which can also be loaded through the video input port or via the i 2 c-bus. it is also possible to encode interlaced 4 :2:2 video signals such as pc-dvd; for that the anti-flicker filter, and in most cases the scaler, will simply be bypassed. besides the applications for video output, the SAA7104E; saa7105e can also be used for generating a kind of auxiliary vga output, when the rgb non-interlaced input signal is fed to the dacs. this may be of interest for example, when the graphics controller provides a second graphics window at its video output port. the basic encoder function consists of subcarrier generation, colour modulation and insertion of synchronization signals at a crystal-stable clock rate of 13.5 mhz (independent of the actual pixel clock used at the input side), corresponding to an internal 4 :2:2 bandwidth in the luminance/colour difference domain. luminance and chrominance signals are filtered in accordance with the standard requirements of rs-170-a and itu-r bt.470-3 . for ease of analog post filtering the signals are twice oversampled to 27 mhz before digital-to-analog conversion. the total filter transfer characteristics (scaler and anti-flicker filter are not taken into account) are illustrated in figs 4 to 9. all three dacs are realized with full 10-bit resolution. the c r -y-c b to rgb dematrix can be bypassed (optionally) in order to provide the upsampled c r -y-c b input signals.
2004 mar 04 10 philips semiconductors product speci?cation digital video encoder SAA7104E; saa7105e the 8-bit multiplexed c b -y-c r formats are itu-r bt.656 (d1 format) compatible, but the sav and eav codes can be decoded optionally, when the device is operated in slave mode. for assignment of the input data to the rising or falling clock edge see tables 9 to 14. in order to display interlaced rgb signals through a euro-connector tv set, a separate digital composite sync signal (pin hsm_csync) can be generated; it can be advanced up to 31 periods of the 27 mhz crystal clock in order to be adapted to the rgb processing of a tv set. the SAA7104E; saa7105e synthesizes all necessary internal signals, colour subcarrier frequency and synchronization signals from that clock. wide screen signalling data can be loaded via the i 2 c-bus and is inserted into line 23 for standards using a 50 hz field rate. vps data for program dependent automatic start and stop of such featured vcrs is loadable via the i 2 c-bus. the ic also contains closed caption and extended data services encoding (line 21), and supports teletext insertion for the appropriate bit stream format at a 27 mhz clock rate (see fig.14). it is also possible to load data for the copy generation management system into line 20 of every field (525/60 line counting). a number of possibilities are provided for setting different video parameters such as: black and blanking level control colour subcarrier frequency variable burst amplitude etc. 7.1 reset conditions to activate the reset a pulse at least of 2 crystal clocks duration is required. during reset ( reset = low) plus an extra 32 crystal clock periods, fsvgc, vsvgc, cbo, hsvgc and ttx_sres are set to input mode and hsm_csync and vsm are set to 3-state. a reset also forces the i 2 c-bus interface to abort any running bus transfer and sets it into receive condition. after reset, the state of the i/os and other functions is defined by the strapping pins until an i 2 c-bus access redefines the corresponding registers; see table 2. table 2 strapping pins 7.2 input formatter the input formatter converts all accepted pd input data formats, either rgb or y-c b -c r , to a common internal rgb or y-c b -c r data stream. when double-edge clocking is used, the data is internally split into portions ppd1 and ppd2. the clock edge assignment must be set according to the i 2 c-bus control bits slot and edge for correct operation. if y-c b -c r is being applied as a 27 mbyte/s data stream, the output of the input formatter can be used directly to feed the video encoder block. the horizontal upscaling is supported via the input formatter. according to the programming of the pixel clock dividers (see section 7.10), it will sample up the data stream to 1 , 2 or 4 the input data rate. an optional interpolation filter is available. the clock domain transition is handled by a 4 entries wide fifo which gets initialized every field or explicitly at request. a bypass for the fifo is available, especially for high input data rates. pin tied preset fsvgc low ntsc m encoding, pixclk ?ts to 640 480 graphics input high pal b/g encoding, pixclk ?ts to 640 480 graphics input vsvgc low 4:2:2 y-c b -c r graphics input (format 0) high 4:4:4 rgb graphics input (format 3) cbo low input demultiplex phase: lsb = low high input demultiplex phase: lsb = high hsvgc low input demultiplex phase: msb = low high input demultiplex phase: msb = high ttxrq_xclko2 low slave (fsvgc, vsvgc and hsvgc are inputs, internal colour bar is active) high master (fsvgc, vsvgc and hsvgc are outputs)
2004 mar 04 11 philips semiconductors product speci?cation digital video encoder SAA7104E; saa7105e 7.3 rgb lut the three 256 byte rams of this block can be addressed by three 8-bit wide signals, thus it can be used to build any transformation, e.g. a gamma correction for rgb signals. in the event that the indexed colour data is applied, the rams are addressed in parallel. the luts can either be loaded by an i 2 c-bus write access or can be part of the pixel data input through the pd port. in the latter case, 256 3 bytes for the r, g and b lut are expected at the beginning of the input video line, two lines before the line that has been defined as first active line, until the middle of the line immediately preceding the first active line. the first 3 bytes represent the first rgb lut data, and so on. 7.4 cursor insertion a32 32 dots cursor can be overlaid as an option; the bit map of the cursor can be uploaded by an i 2 c-bus write access to specific registers or in the pixel data input through the pd port. in the latter case, the 256 bytes defining the cursor bit map (2 bits per pixel) are expected immediately following the last rgb lut data in the line preceding the first active line. the cursor bit map is set up as follows: each pixel occupies 2 bits. the meaning of these bits depends on the cmode i 2 c-bus register as described in table 5. transparent means that the input pixels are passed through, the cursor colours can be programmed in separate registers. the bit map is stored with 4 pixels per byte, aligned to the least significant bit. so the first pixel is in bits 0 and 1, the next pixel in bits 3 and 4 and so on. the first index is the column, followed by the row; index 0,0 is the upper left corner. table 3 layout of a byte in the cursor bit map for each direction, there are 2 registers controlling the position of the cursor, one controls the position of the hot spot, the other register controls the insertion position. the hot spot is the tip of the pointer arrow. it can have any position in the bit map. the actual position registers describe the co-ordinates of the hot spot. again 0,0 is the upper left corner. while it is not possible to move the hot spot beyond the left respectively upper screen border this is perfectly legal for the right respectively lower border. it should be noted that the cursor position is described relative to the input resolution. table 4 cursor bit map table 5 cursor modes d7 d6 d5 d4 d3 d2 d1 d0 pixel n + 3 pixel n + 2 pixel n + 1 pixel n d1 d0 d1 d0 d1 d0 d1 d0 byte d7 d6 d5 d4 d3 d2 d1 d0 0row0 column 3 row 0 column 2 row 0 column 1 row 0 column 0 1row0 column 7 row 0 column 6 row 0 column 5 row 0 column 4 2row0 column 11 row 0 column 10 row 0 column 9 row 0 column 8 ... ... ... ... ... 6row0 column 27 row 0 column 26 row 0 column 25 row 0 column 24 7row0 column 31 row 0 column 30 row 0 column 29 row 0 column 28 ... ... ... ... ... 254 row 31 column 27 row 31 column 26 row 31 column 25 row 31 column 24 255 row 31 column 31 row 31 column 30 row 31 column 29 row 31 column 28 cursor pattern cursor mode cmode = 0 cmode = 1 00 second cursor colour second cursor colour 01 ?rst cursor colour ?rst cursor colour 10 transparent transparent 11 inverted input auxiliary cursor colour
2004 mar 04 12 philips semiconductors product speci?cation digital video encoder SAA7104E; saa7105e 7.5 rgb y-c b -c r matrix rgb input signals to be encoded to pal or ntsc are converted to the y-c b -c r colour space in this block. the colour difference signals are fed through low-pass filters and formatted to a itu-r bt.601 like 4 : 2 : 2 data stream for further processing. a gain adjust option corrects the level swing of the graphics world (black-to-white as 0 to 255) to the required range of 16 to 235. the matrix and formatting blocks can be bypassed for y-c b -c r graphics input. when the auxiliary vga mode is selected, the output of the cursor insertion block is immediately directed to the triple dac. 7.6 horizontal scaler the high quality horizontal scaler operates on the 4 : 2 : 2 data stream. its control engines compensate the colour phase offset automatically. the scaler starts processing after a programmable horizontal offset and continues with a number of input pixels. each input pixel is a programmable fraction of the current output pixel (xinc/4096). a special case is xinc = 0, this sets the scaling factor to 1. if the SAA7104E; saa7105e input data is in accordance with itu-r bt.656 , the scaler enters another mode. in this event, xinc needs to be set to 2048 for a scaling factor of 1. with higher values, upscaling will occur. the phase resolution of the circuit is 12 bits, giving a maximum offset of 0.2 after 800 input pixels. small fifos rearrange a 4 : 2 : 2 data stream at the scaler output. 7.7 vertical scaler and anti-?icker ?lter the functions scaling, anti-flicker filter (aff) and re-interlacing are implemented in the vertical scaler. besides the entire input frame, it receives the first and last lines of the border to allow anti-flicker filtering. the circuit generates the interlaced output fields by scaling down the input frames with different offsets for odd and even fields. increasing the yskip setting reduces the anti-flicker function. a yskip value of 4095 switches it off; see table 86. an additional, programmable vertical filter supports the anti-flicker function. this filter is not available at upscaling factors of more than 2. the programming is similar to the horizontal scaler. for the re-interlacing, the resolutions of the offset registers are not sufficient, so the weighting factors for the first lines can also be adjusted. yinc = 0 sets the scaling factor to 1; yiwgto and yiwgte must not be 0. due to the re-interlacing, the circuit can perform upscaling by a maximum factor of 2. the maximum factor depends on the setting of the anti-flicker function and can be derived from the formulae given in section 7.20. an additional upscaling mode allows to increase the upscaling factor to maximum 4 as it is required for the old vga modes like 320 240. 7.8 fifo the fifo acts as a buffer to translate from the pixclk clock domain to the xtal clock domain. the write clock is pixclk and the read clock is xtal. an underflow or overflow condition can be detected via the i 2 c-bus read access. in order to avoid underflows and overflows, it is essential that the frequency of the synthesized pixclk matches to the input graphics resolution and the desired scaling factor. 7.9 border generator when the graphics picture is to be displayed as interlaced pal, ntsc, s-video or rgb on a tv screen, it is desired in many cases not to lose picture information due to the inherent overscanning of a tv set. the desired amount of underscan area, which is achieved through appropriate scaling in the vertical and horizontal direction, can be filled in the border generator with an arbitrary true colour tint. 7.10 oscillator and discrete time oscillator (dto) the master clock generation is realized as a 27 mhz crystal oscillator, which can operate with either a fundamental wave crystal or a 3rd-harmonic crystal. the crystal clock supplies the dto of the pixel clock synthesizer, the video encoder and the i 2 c-bus control block. it also usually supplies the triple dac, with the exception of the auxiliary vga or hdtv mode, where the triple dac is clocked by the pixel clock (pixclk). the dto can be programmed to synthesize all relevant pixel clock frequencies between circa 40 and 85 mhz. two programmable dividers provide the actual clock to be used externally and internally. the dividers can be programmed to factors of 1, 2, 4 and 8. for the internal pixel clock, a divider ratio of 8 makes no sense and is thus forbidden.
2004 mar 04 13 philips semiconductors product speci?cation digital video encoder SAA7104E; saa7105e the internal clock can be switched completely to the pixel clock input. in this event, the input fifo is useless and will be bypassed. the entire pixel clock generation can be locked to the vertical frequency. both pixel clock dividers get re-initialized every field. optionally, the dto can be cleared with each v-sync. at proper programming, this will make the pixel clock frequency a precise multiple of the vertical and horizontal frequencies. this is required for some graphic controllers. 7.11 low-pass clock generation circuit (cgc) this block reduces the phase jitter of the synthesized pixel clock. it works as a tracking filter for all relevant synthesized pixel clock frequencies. 7.12 encoder 7.12.1 v ideo path the encoder generates luminance and colour subcarrier output signals from the y, c b and c r baseband signals, which are suitable for use as cvbs or separate y and c signals. input to the encoder, at 27 mhz clock (e.g. dvd), is either originated from computer graphics at pixel clock, fed through the fifo and border generator, or a itu-r bt.656 style signal. luminance is modified in gain and in offset (the offset is programmable in a certain range to enable different black level set-ups). a blanking level can be set after insertion of a fixed synchronization pulse tip level, in accordance with standard composite synchronization schemes. other manipulations used for the macrovision anti-taping process, such as additional insertion of agc super-white pulses (programmable in height), are supported by the SAA7104E only. to enable easy analog post filtering, luminance is interpolated from a 13.5 mhz data rate to a 27 mhz data rate, thereby providing luminance in a 10-bit resolution. the transfer characteristics of the luminance interpolation filter are illustrated in figs 6 and 7. appropriate transients at start/end of active video and for synchronization pulses are ensured. chrominance is modified in gain (programmable separately for c b and c r ), and a standard dependent burst is inserted, before baseband colour signals are interpolated from a 6.75 mhz data rate to a 27 mhz data rate. one of the interpolation stages can be bypassed, thus providing a higher colour bandwidth, which can be used for the y and c output. the transfer characteristics of the chrominance interpolation filter are illustrated in figs 4 and 5. the amplitude (beginning and ending) of the inserted burst, is programmable in a certain range that is suitable for standard signals and for special effects. after the succeeding quadrature modulator, colour is provided on the subcarrier in 10-bit resolution. the numeric ratio between the y and c outputs is in accordance with the standards. 7.12.2 t eletext insertion and encoding ( not simultaneously with real - time control ) pin ttx_sres receives a wst or nabts teletext bitstream sampled at the crystal clock. at each rising edge of the output signal (ttxrq) a single teletext bit has to be provided after a programmable delay at input pin ttx_sres. phase variant interpolation is achieved on this bitstream in the internal teletext encoder, providing sufficient small phase jitter on the output text lines. ttxrq_xclko2 provides a fully programmable request signal to the teletext source, indicating the insertion period of bitstream at lines which can be selected independently for both fields. the internal insertion window for text is set to 360 (pal wst), 296 (ntsc wst) or 288 (nabts) teletext bits including clock run-in bits. the protocol and timing are illustrated in fig.14. alternatively, this pin can be provided with a buffered crystal clock (xclk) of 13.5 mhz. 7.12.3 v ideo p rogramming s ystem (vps) encoding five bytes of vps information can be loaded via the i 2 c-bus and will be encoded in the appropriate format into line 16. 7.12.4 c losed c aption encoder using this circuit, data in accordance with the specification of closed caption or extended data service, delivered by the control interface, can be encoded (line 21). two dedicated pairs of bytes (two bytes per field), each pair preceded by run-in clocks and framing code, are possible. the actual line number in which data is to be encoded, can be modified in a certain range. the data clock frequency is in accordance with the definition for ntsc m standard 32 times horizontal line frequency.
2004 mar 04 14 philips semiconductors product speci?cation digital video encoder SAA7104E; saa7105e data low at the output of the dacs corresponds to 0 ire, data high at the output of the dacs corresponds to approximately 50 ire. it is also possible to encode closed caption data for 50 hz field frequencies at 32 times the horizontal line frequency. 7.12.5 a nti - taping (SAA7104E only ) for more information contact your nearest philips semiconductors sales office. 7.13 rgb processor this block contains a dematrix in order to produce red, green and blue signals to be fed to a scart plug. before y, c b and c r signals are de-matrixed, individual gain adjustment for y and colour difference signals and 2 times oversampling for luminance and 4 times oversampling for colour difference signals is performed. the transfer curves of luminance and colour difference components of rgb are illustrated in figs 8 and 9. 7.14 triple dac both y and c signals are converted from digital-to-analog in a 10-bit resolution at the output of the video encoder. y and c signals are also combined into a 10-bit cvbs signal. the cvbs output signal occurs with the same processing delay as the y, c and optional rgb or c r -y-c b outputs. absolute amplitude at the input of the dac for cvbs is reduced by 15 16 with respect to y and c dacs to make maximum use of the conversion ranges. red, green and blue signals are also converted from digital-to-analog, each providing a 10-bit resolution. the reference currents of all three dacs can be adjusted individually in order to adapt for different output signals. in addition, all reference currents can be adjusted commonly to compensate for small tolerances of the on-chip band gap reference voltage. alternatively, all currents can be switched off to reduce power dissipation. all three outputs can be used to sense for an external load (usually 75 w ) during a pre-defined output. a flag in the i 2 c-bus status byte reflects whether a load is applied or not. in addition, an automatic sense mode can be activated which indicates a 75 w load at any of the three outputs at the dedicated interrupt pin tvd. if the SAA7104E; saa7105e is required to drive a second (auxiliary) vga monitor or an hdtv set, the dacs receive the signal coming from the hd data path. in this event, the dacs are clocked at the incoming pixclki instead of the 27 mhz crystal clock used in the video encoder. 7.15 hd data path this data path allows the SAA7104E; saa7105e to be used with vga or hdtv monitors. it receives its data directly from the cursor generator and supports rgb and y-p b -p r output formats (rgb not with y-p b -p r input formats). no scaling is done in this mode. a gain adjustment either leads the full level swing to the digital-to-analog converters or reduces the amplitude by a factor of 0.69. this enables sync pulses to be added to the signal as it is required for display units expecting signals with sync pulses, either regular or 3-level syncs. 7.16 timing generator the synchronization of the SAA7104E; saa7105e is able to operate in two modes; slave mode and master mode. in slave mode, the circuit accepts sync pulses on the bidirectional fsvgc (frame sync), vsvgc (vertical sync) and hsvgc (horizontal sync) pins: the polarities of the signals can be programmed. the frame sync signal is only necessary when the input signal is interlaced, in other cases it may be omitted. if the frame sync signal is present, it is possible to derive the vertical and the horizontal phase from it by setting the hfs and vfs bits. hsvgc and vsvgc are not necessary in this case, so it is possible to switch the pins to output mode. alternatively, the device can be triggered by auxiliary codes in a itu-r bt.656 data stream via pd7 to pd0. only vertical frequencies of 50 and 60 hz are allowed with the SAA7104E; saa7105e. in slave mode, it is not possible to lock the encoders colour carrier to the line frequency with the phres bits. in the (more common) master mode, the time base of the circuit is continuously free-running. the ic can output a frame sync at pin fsvgc, a vertical sync at pin vsvgc, a horizontal sync at pin hsvgc and a composite blanking signal at pin cbo. all of these signals are defined in the pixclk domain. the duration of hsvgc and vsvgc are fixed, they are 64 clocks for hsvgc and 1 line for vsvgc. the leading slopes are in phase and the polarities can be programmed.
2004 mar 04 15 philips semiconductors product speci?cation digital video encoder SAA7104E; saa7105e the input line length can be programmed. the field length is always derived from the field length of the encoder and the pixel clock frequency that is being used. cbo acts as a data request signal. the circuit accepts input data at a programmable number of clocks after cbo goes active. this signal is programmable and it is possible to adjust the following (see figs 12 and 13): the horizontal offset the length of the active part of the line the distance from active start to first expected data the vertical offset separately for odd and even fields the number of lines per input field. in most cases, the vertical offsets for odd and even fields are equal. if they are not, then the even field will start later. the SAA7104E; saa7105e will also request the first input lines in the even field, the total number of requested lines will increase by the difference of the offsets. as stated above, the circuit can be programmed to accept the look-up and cursor data in the first 2 lines of each field. the timing generator provides normal data request pulses for these lines; the duration is the same as for regular lines. the additional request pulses will be suppressed with lutl set to logic 0; see table 109. the other vertical timings do not change in this case, so the first active line can be number 2, counted from 0. 7.17 pattern generator for hd sync pulses the pattern generator provides appropriate synchronization patterns for the video data path in auxiliary monitor or hdtv mode. it provides maximum flexibility in terms of raster generation for all interlaced and non-interlaced computer graphics or atsc formats. the sync engine is capable of providing a combination of event-value pairs which can be used to insert certain values in the outgoing data stream at specified times. it can also be used to generate digital signals associated with time events. these can be used as digital horizontal and vertical synchronization signals on pins hsm_csync and vsm. the picture position is adjustable through the programmable relationship between the sync pulses and the video contents. the generation of embedded analog sync pulses is bound to a number of events which can be defined for a line. several of these line timing definitions can exist in parallel. for the final sync raster composition a certain sequence of lines with different sync event properties has to be defined. the sequence specifies a series of line types and the number of occurrences of this specific line type. once the sequence has been completed, it restarts from the beginning. all pulse shapes are filtered internally in order to avoid ringing after analog post filters. the sequence of the generated pulse stream must fit precisely to the incoming data stream in terms of the total number of pixels per line and lines per frame. the sync engines flexibility is achieved by using a sequence of linked lists carrying the properties for the image, the lines as well as fractions of lines. figure 3 illustrates the context between the various tables. the first table serves as an array to hold the correct sequence of lines that compose the synchronization raster; it can contain up to 16 entries. each entry holds a 4-bit index to the next table and a 10-bit counter value which specifies how often this particular line is invoked. if the necessary line count for a particular line exceeds the 10 bits, it has to use two table entries. the 4-bit index in the line count array points to the line type array. it holds up to 15 entries (index 0 is not used), index 1 points to the first entry, index 2 to the second entry of the line type array etc. each entry of the line type array can hold up to 8 index pointers to another table. these indices point to portions of a line pulse pattern: a line could be split up e.g. into a sync, a blank, and an active portion followed by another blank portion, occupying four entries in one table line. each index of this table points to a particular line of the next table in the linked list. this table is called the line pattern array and each of the up to seven entries stores up to four pairs of a duration in pixel clock cycles and an index to a value table. the table entries are used to define portions of a line representing a certain value for a certain number of clock cycles. the value specified in this table is actually another 3-bit index into a value array which can hold up to eight 8-bit values. if bit 4 (msb) of the index is logic 1, the value is inserted into the g or y signal, only; if bit 4 = 0, the associated value is inserted into all three signals. two additional bits of the entries in the value array (lsbs of the second byte) determine if the associated events appear as a digital pulse on the hsm_csync and/or vsm outputs.
2004 mar 04 16 philips semiconductors product speci?cation digital video encoder SAA7104E; saa7105e 2004 mar 04 16 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... handbook, full pagewidth mhc573 4-bit line type index 10-bit duration 4-bit value index 10-bit line count line count array 16 entries 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 line type array 15 entries value array 8 entries line pattern array 7 entries 8 + 2-bit value 10-bit duration 4-bit value index 10-bit duration 4-bit value index 10-bit duration 4-bit value index line count pointer event type pointer line pattern pointer line type pointer pattern pointer fig.3 context between the pattern generator tables for dh sync pulses.
2004 mar 04 17 philips semiconductors product speci?cation digital video encoder SAA7104E; saa7105e to ease the trigger set-up for the sync generation module, a set of registers is provided to set up the screen raster which is defined as width and height. a trigger position can be specified as an x,y co-ordinate within the overall dimensions of the screen raster. if the x,y counter matches the specified co-ordinates, a trigger pulse is generated which pre-loads the tables with their initial values. the listing in table 6 outlines an example on how to set up the sync tables for a 1080i hd raster. important note: due to a problem in the programming interface, writing to the line pattern array (address d2) might destroy the data of the line type array (address d1). a work around is to write the line pattern array data before writing the line type array. reading of the arrays is possible but all address pointers must be initialized before the next write operation. table 6 example for set-up of the sync tables sequence comment write to subaddress d0h 00 points to ?rst entry of line count array (index 0) 05 20 generate 5 lines of line type index 2 (this is the second entry of the line type array); will be the ?rst vertical raster pulse 01 40 generate 1 line of line type index 4; will be sync-black-sync-black sequence after the ?rst vertical pulse 0e 60 generate 14 lines of line type index 6; will be the following lines with sync-black sequence 1c 12 generate 540 lines of line type index 1; will be lines with sync and active video 02 60 generate 2 lines of line type index 6; will be the following lines with sync-black sequence 01 50 generate 1 line of line type index 5; will be the following line (line 563) with sync-black-sync-black-null sequence (null is equivalent to sync tip) 04 20 generate 4 lines of line type index 2; will be the second vertical raster pulse 01 30 generate 1 line of line type index 3; will be the following line with sync-null-sync-black sequence 0f 60 generate 15 lines of line type index 6; will be the following lines with sync-black sequence 1c 12 generate 540 lines of line type index 1; will be lines with sync and active video 02 60 generate 2 lines of line type index 6; will be the following lines with sync-black sequence; now, 1125 lines are de?ned write to subaddress d2h (insertion is done into all three analog output signals) 00 points to ?rst entry of line pattern array (index 1) 6f 33 2b 30 00 00 00 00 880 value(3) + 44 value(3); (subtract 1 from real duration) 6f 43 2b 30 00 00 00 00 880 value(4) + 44 value(3) 3b 30 bf 03 bf 03 2b 30 60 value(3) + 960 value(0) + 960 value(0) + 44 value(3) 2b 10 2b 20 57 30 00 00 44 value(1) + 44 value(2) + 88 value(3) 3b 30 bf 33 bf 33 2b 30 60 value(3) + 960 value(3) + 960 value(3) + 44 value(3) write to subaddress d1h 00 points to ?rst entry of line type array (index 1) 34 00 00 00 use pattern entries 4 and 3 in this sequence (for sync and active video) 24 24 00 00 use pattern entries 4, 2, 4 and 2 in this sequence (for 2 sync-black-null-black) 24 14 00 00 use pattern entries 4, 2, 4 and 1 in this sequence (for sync-black-null-black-null) 14 14 00 00 use pattern entries 4, 1, 4 and 1 in this sequence (for sync-black-sync-black)
2004 mar 04 18 philips semiconductors product speci?cation digital video encoder SAA7104E; saa7105e 14 24 00 00 use pattern entries 4, 1, 4 and 2 in this sequence (for sync-black-sync-black-null) 54 00 00 00 use pattern entries 4 and 5 in this sequence (for sync-black) write to subaddress d3h (no signals are directed to pins hsm_csync and vsm) 00 points to ?rst entry of value array (index 0) cc 00 black level, to be added during active video 80 00 sync level low (minimum output voltage) 0a 00 sync level high (3-level sync) cc 00 black level (needed elsewhere) 80 00 null (identical to sync level low) write to subaddress dch 0b insertion is active, gain for signal is adapted accordingly sequence comment 7.18 i 2 c-bus interface the i 2 c-bus interface is a standard slave transceiver, supporting 7-bit slave addresses and 400 kbits/s guaranteed transfer rate. it uses 8-bit subaddressing with an auto-increment function. all registers are write and read, except two read only status bytes. the register bit map consists of an rgb look-up table (lut), a cursor bit map and control registers. the lut contains three banks of 256 bytes, where each rgb triplet is assigned to one address. thus a write access needs the lut address and three data bytes following subaddress ffh. for further write access auto-incrementing of the lut address is performed. the cursor bit map access is similar to the lut access but contains only a single byte per address. the i 2 c-bus slave address is defined as 88h. 7.19 power-down modes in order to reduce the power consumption, the SAA7104E; saa7105e supports 2 power-down modes, accessible via the i 2 c-bus. the analog power-down mode (downa = 1) turns off the digital-to-analog converters and the pixel clock synthesizer. the digital power-down mode turns off all internal clocks and sets the digital outputs to low except the i 2 c-bus interface. the ic keeps its programming and can still be accessed in this mode, however not all registers can be read or written to. reading or writing to the look-up tables, the cursor and the hd sync generator require a valid pixel clock. the typical supply current in full power-down is approximately 5 ma. because the analog power-down mode turns off the pixel clock synthesizer, there are limitations in some applications. if there is no pixel clock, the ic is not able to set its outputs to low. so, in most cases, downa and downd should be set to logic 1 simultaneously. if the eidiv bit is logic 1, it should be set to logic 0 before power-down. 7.20 programming the SAA7104E; saa7105e the SAA7104E; saa7105e needs to provide a continuous data stream at its analog outputs as well as receive a continuous stream of data from its data source. because there is no frame memory isolating the data streams, restrictions apply to the input frame timings. input and output processing of the SAA7104E; saa7105e are only coupled through the vertical frequencies. in master mode, the encoder provides a vertical sync and an odd/even pulse to the input processing. in slave mode, the encoder receives them. the parameters of the input field are mainly given by the memory capacity of the SAA7104E; saa7105e. the rule is that the scaler and thus the input processing needs to provide the video data in the same time frames as the encoder reads them. therefore, the vertical active video times (and the vertical frequencies) need to be the same. the second rule is that there has to be data in the buffer fifo when the encoder enters the active video area. therefore, the vertical offset in the input path needs to be a bit shorter than the offset of the encoder.
2004 mar 04 19 philips semiconductors product speci?cation digital video encoder SAA7104E; saa7105e the following sections give the set of equations required to program the ic for the most common application: a post processor in master mode with non-interlaced video input data. some variables are defined below: inpix: the number of active pixels per input line inppl: the length of the entire input line in pixel clocks inlin: the number of active lines per input field/frame tpclk: the pixel clock period riepclk: the ratio of internal to external pixel clock outpix: the number of active pixels per output line outlin: the number of active lines per output field txclk: the encoder clock period (37.037 ns). 7.20.1 tv display window at 60 hz, the first visible pixel has the index 256, 710 pixels can be encoded; at 50 hz, the index is 284, 702 pixels can be visible. the output lines should be centred on the screen. it should be noted that the encoder has 2 clocks per pixel; see table 59. adwhs = 256 + 710 - outpix (60 hz); adwhs = 284 + 702 - outpix (50 hz); adwhe = adwhs + outpix 2 (all frequencies) for vertical, the procedure is the same. at 60 hz, the first line with video information is number 19, 240 lines can be active. for 50 hz, the numbers are 23 and 287; see table 65. (60 hz); (50 hz); lal = fal + outlin (all frequencies) most tv sets use overscan, and not all pixels respectively lines are visible. there is no standard for the factor, it is highly recommended to make the number of output pixels and lines adjustable. a reasonable underscan factor is 10%, giving approximately 640 output pixels per line. 7.20.2 i nput frame and pixel clock the total number of pixel clocks per line and the input horizontal offset need to be chosen next. the only constraint is that the horizontal blanking has at least 10 clock pulses. the required pixel clock frequency can be determined in the following way: due to the limited internal fifo size, the input path has to provide all pixels in the same time frame as the encoders vertical active time. the scaler also has to process the first and last border lines for the anti-flicker function. thus: (60 hz) (50 hz) and for the pixel clock generator (all frequencies); see tables 68, 70 and 71. the divider pcle should be set according to table 70. pcli may be set to a lower or the same value. setting a lower value means that the internal pixel clock is higher and the data get sampled up. the difference may be 1 at 640 480 pixels resolution and 2 at resolutions with 320 pixels per line as a rule of thumb. this allows horizontal upscaling by a maximum factor of 2 respectively 4 (this is the parameter riepclk). (all frequencies) the equations ensure that the last line of the field has the full number of clock cycles. many graphic controllers require this. note that the bit pclsy needs to be set to ensure that there is not even a fraction of a clock left at the end of the field. 7.20.3 h orizontal scaler xofs can be chosen arbitrarily, the condition being that xofs + xpix hlen is fulfilled. values given by the vesa display timings are preferred. hlen = inppl riepclk - 1 xinc needs to be rounded up, it needs to be set to 0 for a scaling factor of 1. fal 19 240 outlin C 2 --------------------------------- + = fal 23 287 outlin C 2 --------------------------------- + = tpclk 262.5 1716 txclk inppl integer inlin 2 + outlin ---------------------- 262.5 ? ?? ---------------------------------------------------------------------------------------- = tpclk 312.5 1728 txclk inppl integer inlin 2 + outlin ---------------------- 312.5 ? ?? ---------------------------------------------------------------------------------------- = pcl txclk tpclk -------------- - 2 20 pcle + = pcli pcle riepclk log 2 log ---------------------------- C = xpix inpix 2 ------------ - riepclk = xinc outpix inpix ----------------- - 4096 riepclk ------------------- - =
2004 mar 04 20 philips semiconductors product speci?cation digital video encoder SAA7104E; saa7105e 7.20.4 v ertical scaler the input vertical offset can be taken from the assumption that the scaler should just have finished writing the first line when the encoder starts reading it: (60 hz) (50 hz) in most cases the vertical offsets will be the same for odd and even fields. the results should be rounded down. ypix = inlin yskip defines the anti-flicker function. 0 means maximum flicker reduction but minimum vertical bandwidth, 4095 gives no flicker reduction and maximum bandwidth. note that the maximum value for yinc is 4095. it might be necessary to reduce the value of yskip to fulfil this requirement. when yinc = 0 it sets the scaler to scaling factor 1. the initial weighting factors must not be set to 0 in this case. yiwgte may go negative. in this event, yinc should be added and yofse incremented. this can be repeated as often as necessary to make yiwgte positive. it should be noted that these equations assume that the input is non-interlaced but the output is interlaced. if the input is interlaced, the initial weighting factors need to be adapted to obtain the proper phase offsets in the output frame. if vertical upscaling beyond the upper capabilities is required, the parameter yupsc may be set to logic 1. this extends the maximum vertical scaling factor by a factor of 2. only the parameter yinc is affected, it needs to be divided by two to get the same effect. there are restrictions in this mode: the vertical filter yfilt is not available in this mode; the circuit will ignore this value the horizontal blanking needs to be long enough to transfer an output line between 2 memory locations. this is 710 internal pixel clocks. or the upscaling factor needs to be limited to 1.5 and the horizontal upscaling factor is also limited to less than ~ 1.5. in this case a normal blanking length is sufficient. 7.21 input levels and formats the SAA7104E; saa7105e accepts digital y, c b ,c r or rgb data with levels (digital codes) in accordance with itu-r bt.601 . an optional gain adjustment also allows to accept data with the full level swing of 0 to 255. for c and cvbs outputs, deviating amplitudes of the colour difference signals can be compensated for by independent gain control setting, while gain for luminance is set to predefined values, distinguishable for 7.5 ire set-up or without set-up. the rgb, respectively c r -y-c b path features an individual gain setting for luminance (gy) and colour difference signals (gcd). reference levels are measured with a colour bar, 100% white, 100% amplitude and 100% saturation. the SAA7104E; saa7105e has special input cells for the vgc port. they operate at a wider supply voltage range and have a strict input threshold at 1 / 2 v ddd . to achieve full speed of these cells, the eidiv bit needs to be set to logic 1. note that the impedance of these cells is approximately 6 k w . this may cause trouble with the bootstrapping pins of some graphic chips. so the power-on reset forces the bit to logic 0, the input impedance is regular in this mode. table 7 itu-r bt.601 signal component levels note 1. transformation: a) r = y + 1.3707 (c r - 128) b) g = y - 0.3365 (c b - 128) - 0.6982 (c r - 128) c) b = y + 1.7324 (c b - 128). yofs fal 1716 txclk inppl tpclk --------------------------------------------------- - 2.5 C = yofs fal 1728 txclk inppl tpclk --------------------------------------------------- - 2.5 C = yinc outlin inlin 2 + ---------------------- 1 yskip 4095 ----------------- + ? ?? 4096 = yiwgto yinc 2 ------------- - 2048 + = yiwgte yinc yskip C 2 ------------------------------------- - = colour signals (1) yc b c r rgb white 235 128 128 235 235 235 yellow 210 16 146 235 235 16 cyan 170 166 16 16 235 235 green 145 54 34 16 235 16 magenta 106 202 222 235 16 235 red 81 90 240 235 16 16 blue 41 240 110 16 16 235 black 16 128 128 16 16 16
2004 mar 04 21 philips semiconductors product speci?cation digital video encoder SAA7104E; saa7105e table 8 usage of bits slot and edge table 9 pin assignment for input format 0 table 10 pin assignment for input format 1 table 11 pin assignment for input format 2 table 12 pin assignment for input format 3 data slot control (example for format 0) slot edge 1st data 2nd data 0 0 at rising edge g3/y3 at falling edge r7/c r 7 0 1 at falling edge g3/y3 at rising edge r7/c r 7 1 0 at rising edge r7/c r 7 at falling edge g3/y3 1 1 at falling edge r7/c r 7 at rising edge g3/y3 8 + 8 + 8-bit 4 : 4 : 4 non-interlaced rgb/c b -y-c r pin falling clock edge rising clock edge pd11 g3/y3 r7/c r 7 pd10 g2/y2 r6/c r 6 pd9 g1/y1 r5/c r 5 pd8 g0/y0 r4/c r 4 pd7 b7/c b 7 r3/c r 3 pd6 b6/c b 6 r2/c r 2 pd5 b5/c b 5 r1/c r 1 pd4 b4/c b 4 r0/c r 0 pd3 b3/c b 3 g7/y7 pd2 b2/c b 2 g6/y6 pd1 b1/c b 1 g5/y5 pd0 b0/c b 0 g4/y4 5 + 5 + 5-bit 4 : 4 : 4 non-interlaced rgb pin falling clock edge rising clock edge pd7 g2 x pd6 g1 r4 pd5 g0 r3 pd4 b4 r2 pd3 b3 r1 pd2 b2 r0 pd1 b1 g4 pd0 b0 g3 5 + 6 + 5-bit 4 : 4 : 4 non-interlaced rgb pin falling clock edge rising clock edge pd7 g2 r4 pd6 g1 r3 pd5 g0 r2 pd4 b4 r1 pd3 b3 r0 pd2 b2 g5 pd1 b1 g4 pd0 b0 g3 8 + 8 + 8-bit 4:2:2 non-interlaced c b -y-c r pin falling clock edge n rising clock edge n falling clock edge n+1 rising clock edge n+1 pd7 c b 7(0) y7(0) c r 7(0) y7(1) pd6 c b 6(0) y6(0) c r 6(0) y6(1) pd5 c b 5(0) y5(0) c r 5(0) y5(1) pd4 c b 4(0) y4(0) c r 4(0) y4(1) pd3 c b 3(0) y3(0) c r 3(0) y3(1) pd2 c b 2(0) y2(0) c r 2(0) y2(1) pd1 c b 1(0) y1(0) c r 1(0) y1(1) pd0 c b 0(0) y0(0) c r 0(0) y0(1)
2004 mar 04 22 philips semiconductors product speci?cation digital video encoder SAA7104E; saa7105e table 13 pin assignment for input format 4 table 14 pin assignment for input format 5; note 1 note 1. x = dont care. table 15 pin assignment for input format 6 8 + 8 + 8-bit 4 : 2 : 2 interlaced c b -y-c r (itu-r bt.656, 27 mhz clock) pin rising clock edge n rising clock edge n+1 rising clock edge n+2 rising clock edge n+3 pd7 c b 7(0) y7(0) c r 7(0) y7(1) pd6 c b 6(0) y6(0) c r 6(0) y6(1) pd5 c b 5(0) y5(0) c r 5(0) y5(1) pd4 c b 4(0) y4(0) c r 4(0) y4(1) pd3 c b 3(0) y3(0) c r 3(0) y3(1) pd2 c b 2(0) y2(0) c r 2(0) y2(1) pd1 c b 1(0) y1(0) c r 1(0) y1(1) pd0 c b 0(0) y0(0) c r 0(0) y0(1) 8-bit non-interlaced index colour pin falling clock edge rising clock edge pd11 x x pd10 x x pd9 x x pd8 x x pd7 index7 x pd6 index6 x pd5 index5 x pd4 index4 x pd3 index3 x pd2 index2 x pd1 index1 x pd0 index0 x 8 + 8 + 8-bit 4 : 4 : 4 non-interlaced rgb/c b -y-c r pin falling clock edge rising clock edge pd11 g4/y4 r7/c r 7 pd10 g3/y3 r6/c r 6 pd9 g2/y2 r5/c r 5 pd8 b7/c b 7 r4/c r 4 pd7 b6/c b 6 r3/c r 3 pd6 b5/c b 5 g7/y7 pd5 b4/c b 4 g6/y6 pd4 b3/c b 3 g5/y5 pd3 g0/y0 r2/c r 2 pd2 b2/c b 2 r1/c r 1 pd1 b1/c b 1 r0/c r 0 pd0 b0/c b 0 g1/y1
2004 mar 04 23 philips semiconductors product speci?cation digital video encoder SAA7104E; saa7105e 2004 mar 04 23 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 7.22 bit allocation map table 16 slave receiver (slave address 88h) register function sub addr. (hex) d7 d6 d5 d4 d3 d2 d1 d0 status byte (read only) 00 ver2 ver1 ver0 ccrdo ccrde (1) fseq o_e null 01 to 15 (1) (1) (1) (1) (1) (1) (1) (1) common dac adjust ?ne 16 (1) (1) (1) (1) dacf3 dacf2 dacf1 dacf0 r dac adjust coarse 17 (1) (1) (1) rdacc4 rdacc3 rdacc2 rdacc1 rdacc0 g dac adjust coarse 18 (1) (1) (1) gdacc4 gdacc3 gdacc2 gdacc1 gdacc0 b dac adjust coarse 19 (1) (1) (1) bdacc4 bdacc3 bdacc2 bdacc1 bdacc0 msm threshold 1a msmt7 msmt6 msmt5 msmt4 msmt3 msmt2 msmt1 msmt0 monitor sense mode 1b msm msa msoe (1) (1) rcomp gcomp bcomp chip id (02b or 03b, read only) 1c cid7 cid6 cid5 cid4 cid3 cid2 cid1 cid0 wide screen signal 26 wss7 wss6 wss5 wss4 wss3 wss2 wss1 wss0 wide screen signal 27 wsson (1) wss13 wss12 wss11 wss10 wss9 wss8 real-time control, burst start 28 (1) (1) bs5 bs4 bs3 bs2 bs1 bs0 sync reset enable, burst end 29 sres (1) be5 be4 be3 be2 be1 be0 copy generation 0 2a cg07 cg06 cg05 cg04 cg03 cg02 cg01 cg00 copy generation 1 2b cg15 cg14 cg13 cg12 cg11 cg10 cg09 cg08 cg enable, copy generation 2 2c cgen (1) (1) (1) cg19 cg18 cg17 cg16 output port control 2d vbsen cvbsen1 cvbsen0 cen encoff clk2en cvbsen2 (1) null 2e to 36 (1) (1) (1) (1) (1) (1) (1) (1) input path control 37 (1) yupsc yfil1 yfil0 (1) czoom igain xint gain luminance for rgb 38 (1) (1) (1) gy4 gy3 gy2 gy1 gy0 gain colour difference for rgb 39 (1) (1) (1) gcd4 gcd3 gcd2 gcd1 gcd0 input port control 1 3a cbenb (1) syntv symp demoff csync y2c uv2c vps enable, input control 2 54 vpsen (1) gpval gpen (1) (1) edge slot vps byte 5 55 vps57 vps56 vps55 vps54 vps53 vps52 vps51 vps50 vps byte 11 56 vps117 vps116 vps115 vps114 vps113 vps112 vps111 vps110 vps byte 12 57 vps127 vps126 vps125 vps124 vps123 vps122 vps121 vps120 vps byte 13 58 vps137 vps136 vps135 vps134 vps133 vps132 vps131 vps130 vps byte 14 59 vps147 vps146 vps145 vps144 vps143 vps142 vps141 vps140 chrominance phase 5a chps7 chps6 chps5 chps4 chps3 chps2 chps1 chps0
2004 mar 04 24 philips semiconductors product speci?cation digital video encoder SAA7104E; saa7105e 2004 mar 04 24 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... gain u 5b gainu7 gainu6 gainu5 gainu4 gainu3 gainu2 gainu1 gainu0 gain v 5c gainv7 gainv6 gainv5 gainv4 gainv3 gainv2 gainv1 gainv0 gain u msb, black level 5d gainu8 (1) blckl5 blckl4 blckl3 blckl2 blckl1 blckl0 gain v msb, blanking level 5e gainv8 (1) blnnl5 blnnl4 blnnl3 blnnl2 blnnl1 blnnl0 ccr, blanking level vbi 5f ccrs1 ccrs0 blnvb5 blnvb4 blnvb3 blnvb2 blnvb1 blnvb0 null 60 (1) (1) (1) (1) (1) (1) (1) (1) standard control 61 downd downa inpi ygs (1) scbw pal fise burst amplitude 62 rtce bsta6 bsta5 bsta4 bsta3 bsta2 bsta1 bsta0 subcarrier 0 63 fsc07 fsc06 fsc05 fsc04 fsc03 fsc02 fsc01 fsc00 subcarrier 1 64 fsc15 fsc14 fsc13 fsc12 fsc11 fsc10 fsc09 fsc08 subcarrier 2 65 fsc23 fsc22 fsc21 fsc20 fsc19 fsc18 fsc17 fsc16 subcarrier 3 66 fsc31 fsc30 fsc29 fsc28 fsc27 fsc26 fsc25 fsc24 line 21 odd 0 67 l21o07 l21o06 l21o05 l21o04 l21o03 l21o02 l21o01 l21o00 line 21 odd 1 68 l21o17 l21o16 l21o15 l21o14 l21o13 l21o12 l21o11 l21o10 line 21 even 0 69 l21e07 l21e06 l21e05 l21e04 l21e03 l21e02 l21e01 l21e00 line 21 even 1 6a l21e17 l21e16 l21e15 l21e14 l21e13 l21e12 l21e11 l21e10 null 6b (1) (1) (1) (1) (1) (1) (1) (1) trigger control 6c htrig7 htrig6 htrig5 htrig4 htrig3 htrig2 htrig1 htrig0 trigger control 6d htrig10 htrig9 htrig8 vtrig4 vtrig3 vtrig2 vtrig1 vtrig0 multi control 6e nvtrig blckon phres1 phres0 ldel1 ldel0 flc1 flc0 closed caption, teletext enable 6f ccen1 ccen0 ttxen sccln4 sccln3 sccln2 sccln1 sccln0 active display window horizontal start 70 adwhs7 adwhs6 adwhs5 adwhs4 adwhs3 adwhs2 adwhs1 adwhs0 active display window horizontal end 71 adwhe7 adwhe6 adwhe5 adwhe4 adwhe3 adwhe2 adwhe1 adwhe0 msbs adwh 72 (1) adwhe10 adwhe9 adwhe8 (1) adwhs10 adwhs9 adwhs8 ttx request horizontal start 73 ttxhs7 ttxhs6 ttxhs5 ttxhs4 ttxhs3 ttxhs2 ttxhs1 ttxhs0 ttx request horizontal delay 74 (1) (1) (1) (1) ttxhd3 ttxhd2 ttxhd1 ttxhd0 csync advance 75 csynca4 csynca3 csynca2 csynca1 csynca0 (1) (1) (1) ttx odd request vertical start 76 ttxovs7 ttxovs6 ttxovs5 ttxovs4 ttxovs3 ttxovs2 ttxovs1 ttxovs0 ttx odd request vertical end 77 ttxove7 ttxove6 ttxove5 ttxove4 ttxove3 ttxove2 ttxove1 ttxove0 ttx even request vertical start 78 ttxevs7 ttxevs6 ttxevs5 ttxevs4 ttxevs3 ttxevs2 ttxevs1 ttxevs0 register function sub addr. (hex) d7 d6 d5 d4 d3 d2 d1 d0
2004 mar 04 25 philips semiconductors product speci?cation digital video encoder SAA7104E; saa7105e 2004 mar 04 25 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... ttx even request vertical end 79 ttxeve7 ttxeve6 ttxeve5 ttxeve4 ttxeve3 ttxeve2 ttxeve1 ttxeve0 first active line 7a fal7 fal6 fal5 fal4 fal3 fal2 fal1 fal0 last active line 7b lal7 lal6 lal5 lal4 lal3 lal2 lal1 lal0 ttx mode, msb vertical 7c ttx60 lal8 ttxo fal8 ttxeve8 ttxove8 ttxevs8 ttxovs8 null 7d (1) (1) (1) (1) (1) (1) (1) (1) disable ttx line 7e line12 line11 line10 line9 line8 line7 line6 line5 disable ttx line 7f line20 line19 line18 line17 line16 line15 line14 line13 fifo status (read only) 80 (1) (1) (1) (1) iferr bferr ovfl udfl pixel clock 0 81 pcl07 pcl06 pcl05 pcl04 pcl03 pcl02 pcl01 pcl00 pixel clock 1 82 pcl15 pcl14 pcl13 pcl12 pcl11 pcl10 pcl09 pcl08 pixel clock 2 83 pcl23 pcl22 pcl21 pcl20 pcl19 pcl18 pcl17 pcl16 pixel clock control 84 dclk pclsy ifra ifbp pcle1 pcle0 pcli1 pcli0 fifo control 85 eidiv (1) (1) (1) fili3 fili2 fili1 fili0 null 86 to 8f (1) (1) (1) (1) (1) (1) (1) (1) horizontal offset 90 xofs7 xofs6 xofs5 xofs4 xofs3 xofs2 xofs1 xofs0 pixel number 91 xpix7 xpix6 xpix5 xpix4 xpix3 xpix2 xpix1 xpix0 vertical offset odd 92 yofso7 yofso6 yofso5 yofso4 yofso3 yofso2 yofso1 yofso0 vertical offset even 93 yofse7 yofse6 yofse5 yofse4 yofse3 yofse2 yofse1 yofse0 msbs 94 yofse9 yofse8 yofso9 yofso8 xpix9 xpix8 xofs9 xofs8 line number 95 ypix7 ypix6 ypix5 ypix4 ypix3 ypix2 ypix1 ypix0 scaler ctrl, mcb ypix 96 efs pcbn slave ilc yfil (1) ypix9 ypix8 sync control 97 hfs vfs ofs pfs ovs pvs ohs phs line length 98 hlen7 hlen6 hlen5 hlen4 hlen3 hlen2 hlen1 hlen0 input delay, msb line length 99 idel3 idel2 idel1 idel0 hlen11 hlen10 hlen9 hlen8 horizontal increment 9a xinc7 xinc6 xinc5 xinc4 xinc3 xinc2 xinc1 xinc0 vertical increment 9b yinc7 yinc6 yinc5 yinc4 yinc3 yinc2 yinc1 yinc0 msbs vertical and horizontal increment 9c yinc11 yinc10 yinc9 yinc8 xinc11 xinc10 xinc9 xinc8 weighting factor odd 9d yiwgto7 yiwgto6 yiwgto5 yiwgto4 yiwgto3 yiwgto2 yiwgto1 yiwgto0 weighting factor even 9e yiwgte7 yiwgte6 yiwgte5 yiwgte4 yiwgte3 yiwgte2 yiwgte1 yiwgte0 weighting factor msb 9f yiwgte11 yiwgte10 yiwgte9 yiwgte8 yiwgto11 yiwgto10 yiwgto9 yiwgto8 vertical line skip a0 yskip7 yskip6 yskip5 yskip4 yskip3 yskip2 yskip1 yskip0 register function sub addr. (hex) d7 d6 d5 d4 d3 d2 d1 d0
2004 mar 04 26 philips semiconductors product speci?cation digital video encoder SAA7104E; saa7105e 2004 mar 04 26 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... blank enable for ni-bypass, vertical line skip msb a1 blen (1) (1) (1) yskip11 yskip10 yskip9 yskip8 border colour y a2 bcy7 bcy6 bcy5 bcy4 bcy3 bcy2 bcy1 bcy0 border colour u a3 bcu7 bcu6 bcu5 bcu4 bcu3 bcu2 bcu1 bcu0 border colour v a4 bcv7 bcv6 bcv5 bcv4 bcv3 bcv2 bcv1 bcv0 hd sync line count array d0 ram address (see table 89) hd sync line type array d1 ram address (see table 91) hd sync line pattern array d2 ram address (see table 93) hd sync value array d3 ram address (see table 95) hd sync trigger state 1 d4 hlct7 hlct6 hlct5 hlct4 hlct3 hlct2 hlct1 hlct0 hd sync trigger state 2 d5 hlcpt3 hlcpt2 hlcpt1 hlcpt0 hlppt1 hlppt0 hlct9 hlct8 hd sync trigger state 3 d6 hdct7 hdct6 hdct5 hdct4 hdct3 hdct2 hdct1 hdct0 hd sync trigger state 4 d7 (1) hept2 hept1 hept0 (1) (1) hdct9 hdct8 hd sync trigger phase x d8 htx7 htx6 htx5 htx4 htx3 htx2 htx1 htx0 d9 (1) (1) (1) (1) htx11 htx10 htx9 htx8 hd sync trigger phase y da hty7 hty6 hty5 hty4 hty3 hty2 hty1 hty0 db (1) (1) (1) (1) (1) (1) hty9 hty8 hd output control dc (1) (1) (1) (1) hdsye hdtc hdgy hdip cursor colour 1 r f0 cc1r7 cc1r6 cc1r5 cc1r4 cc1r3 cc1r2 cc1r1 cc1r0 cursor colour 1 g f1 cc1g7 cc1g6 cc1g5 cc1g4 cc1g3 cc1g2 cc1g1 cc1g0 cursor colour 1 b f2 cc1b7 cc1b6 cc1b5 cc1b4 cc1b3 cc1b2 cc1b1 cc1b0 cursor colour 2 r f3 cc2r7 cc2r6 cc2r5 cc2r4 cc2r3 cc2r2 cc2r1 cc2r0 cursor colour 2 g f4 cc2g7 cc2g6 cc2g5 cc2g4 cc2g3 cc2g2 cc2g1 cc2g0 cursor colour 2 b f5 cc2b7 cc2b6 cc2b5 cc2b4 cc2b3 cc2b2 cc2b1 cc2b0 auxiliary cursor colour r f6 auxr7 auxr6 auxr5 auxr4 auxr3 auxr2 auxr1 auxr0 auxiliary cursor colour g f7 auxg7 auxg6 auxg5 auxg4 auxg3 auxg2 auxg1 auxg0 auxiliary cursor colour b f8 auxb7 auxb6 auxb5 auxb4 auxb3 auxb2 auxb1 auxb0 horizontal cursor position f9 xcp7 xcp6 xcp5 xcp4 xcp3 xcp2 xcp1 xcp0 horizontal hot spot, msb xcp fa xhs4 xhs3 xhs2 xhs1 xhs0 xcp10 xcp9 xcp8 vertical cursor position fb ycp7 ycp6 ycp5 ycp4 ycp3 ycp2 ycp1 ycp0 vertical hot spot, msb ycp fc yhs4 yhs3 yhs2 yhs1 yhs0 (1) ycp9 ycp8 register function sub addr. (hex) d7 d6 d5 d4 d3 d2 d1 d0
2004 mar 04 27 philips semiconductors product speci?cation digital video encoder SAA7104E; saa7105e 2004 mar 04 27 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... note 1. all unused control bits must be programmed with logic 0 to ensure compatibility to future enhancements. input path control fd lutoff cmode lutl if2 if1 if0 matoff dfoff cursor bit map fe ram address (see table 110) colour look-up table ff ram address (see table 111) register function sub addr. (hex) d7 d6 d5 d4 d3 d2 d1 d0
2004 mar 04 28 philips semiconductors product speci?cation digital video encoder SAA7104E; saa7105e 7.23 i 2 c-bus format table 17 i 2 c-bus write access to control registers; see table 23 table 18 i 2 c-bus write access to the hd line count array (subaddress d0h); see table 23 table 19 i 2 c-bus write access to cursor bit map (subaddress feh); see table 23 table 20 i 2 c-bus write access to colour look-up table (subaddress ffh); see table 23 table 21 i 2 c-bus read access to control registers; see table 23 table 22 i 2 c-bus read access to cursor bit map or colour lut; see table 23 table 23 explanations of tables 17 to 22 notes 1. x is the read/write control bit; x = logic 0 is order to write; x = logic 1 is order to read. 2. if more than 1 byte of data is transmitted, then auto-increment of the subaddress is performed. s 10001000 a subaddress a data 0 a -------- data n a p s 10001000 a d0h a ram address a data 00 a data 01 a -------- data n a p s 10001000 a feh a ram address a data 0 a -------- data n a p s 10001000 a ffh a ram address a data 0r a data 0g a data 0b a -------- p s 10001000 a subaddress a sr 10001001 a data0 am -------- data n am p s 10001000 a feh or ffh a ram address a sr 1 0 001001 a data0 am -------- data n am p code description s start condition sr repeated start condition 1000100x; note 1 slave address a acknowledge generated by the slave am acknowledge generated by the master subaddress; note 2 subaddress byte data data byte -------- continued data bytes and acknowledges p stop condition ram address start address for ram access
2004 mar 04 29 philips semiconductors product speci?cation digital video encoder SAA7104E; saa7105e 7.24 slave receiver table 24 subaddress 16h table 25 fine adjustment of dac output voltage table 26 subaddresses 17h to 19h table 27 subaddress 1ah data byte description dacf output level adjustment ?ne in 1% steps for all dacs; default after reset is 00h; see table 25 binary gain (%) 0111 7 0110 6 0101 5 0100 4 0011 3 0010 2 0001 1 0000 0 1000 0 1001 - 1 1010 - 2 1011 - 3 1100 - 4 1101 - 5 1110 - 6 1111 - 7 data byte description rdacc output level coarse adjustment for red dac; default after reset is 1bh for output of c signal 00000b o 0.585 v to 11111b o 1.240 v at 37.5 w nominal for full-scale conversion gdacc output level coarse adjustment for green dac; default after reset is 1bh for output of vbs signal 00000b o 0.585 v to 11111b o 1.240 v at 37.5 w nominal for full-scale conversion bdacc output level coarse adjustment for blue dac; default after reset is 1fh for output of cvbs signal 00000b o 0.585 v to 11111b o 1.240 v at 37.5 w nominal for full-scale conversion data byte description msmt monitor sense mode threshold for dac output voltage, should be set to 70
2004 mar 04 30 philips semiconductors product speci?cation digital video encoder SAA7104E; saa7105e table 28 subaddress 1bh table 29 subaddresses 26h and 27h table 30 subaddress 28h data byte logic level description msm 0 monitor sense mode off; rcomp, gcomp and bcomp bits are not valid; default after reset 1 monitor sense mode on msa 0 automatic monitor sense mode off; rcomp, gcomp and bcomp bits are not valid; default after reset 1 automatic monitor sense mode on if msm = 0 msoe 0 pin tvd is active 1 pin tvd is 3-state; default after reset rcomp (read only) 0 check comparator at dac on pin red_cr_c_cvbs is active, output is loaded 1 check comparator at dac on pin red_cr_c_cvbs is inactive, output is not loaded gcomp (read only) 0 check comparator at dac on pin green_vbs_cvbs is active, output is loaded 1 check comparator at dac on pin green_vbs_cvbs is inactive, output is not loaded bcomp (read only) 0 check comparator at dac on pin blue_cb_cvbs is active, output is loaded 1 check comparator at dac on pin blue_cb_cvbs is inactive, output is not loaded data byte logic level description wss - wide screen signalling bits 3 to 0 = aspect ratio 7 to 4 = enhanced services 10 to 8 = subtitles 13 to 11 = reserved wsson 0 wide screen signalling output is disabled; default after reset 1 wide screen signalling output is enabled data byte logic level description remarks bs - starting point of burst in clock cycles pal: bs = 33 (21h); default after reset if strapping pin fsvgc tied to high ntsc: bs = 25 (19h); default after reset if strapping pin fsvgc tied to low
2004 mar 04 31 philips semiconductors product speci?cation digital video encoder SAA7104E; saa7105e table 31 subaddress 29h table 32 subaddresses 2ah to 2ch table 33 subaddress 2dh data byte logic level description remarks sres 0 pin ttx_sres accepts a teletext bit stream (ttx) default after reset 1 pin ttx_sres accepts a sync reset input (sres) a high impulse resets synchronization of the encoder (?rst ?eld, ?rst line) be - ending point of burst in clock cycles pal: be = 29 (1dh); default after reset if strapping pin fsvgc tied to high ntsc: be = 29 (1dh); default after reset if strapping pin fsvgc tied to low data byte logic level description cg - lsbs of the respective bytes are encoded immediately after run-in, the msbs of the respective bytes have to carry the crcc bits, in accordance with the de?nition of copy generation management system encoding format. cgen 0 copy generation data output is disabled; default after reset 1 copy generation data output is enabled data byte logic level description vbsen 0 pin green_vbs_cvbs provides a component green signal (cvbsen1 = 0) or cvbs signal (cvbsen1 = 1) 1 pin green_vbs_cvbs provides a luminance (vbs) signal; default after reset cvbsen1 0 pin green_vbs_cvbs provides a component green (g) or luminance (vbs) signal; default after reset 1 pin green_vbs_cvbs provides a cvbs signal cvbsen0 0 pin blue_cb_cvbs provides a component blue (b) or colour difference blue (c b ) signal 1 pin blue_cb_cvbs provides a cvbs signal; default after reset cen 0 pin red_cr_c_cvbs provides a component red (r) or colour difference red (c r ) signal 1 pin red_cr_c_cvbs provides a chrominance signal (c) as modulated subcarrier for s-video; default after reset encoff 0 encoder is active; default after reset 1 encoder bypass, dacs are provided with rgb signal after cursor insertion block clk2en 0 pin ttxrq_xclko2 provides a teletext request signal (ttxrq) 1 pin ttxrq_xclko2 provides the buffered crystal clock divided by two (13.5 mhz); default after reset cvbsen2 0 pin red_cr_c_cvbs provides a signal according to cen; default after reset 1 pin red_cr_c_cvbs provides a cvbs signal
2004 mar 04 32 philips semiconductors product speci?cation digital video encoder SAA7104E; saa7105e table 34 subaddress 37h table 35 logic levels and function of yfil table 36 subaddresses 38h and 39h data byte logic level description yupsc 0 normal operation of the vertical scaler; default after reset 1 vertical upscaling is enabled yfil - controls the vertical interpolation ?lter, see table 35; the ?lter is not available if yupsc = 1 czoom 0 normal operation of the cursor generator; default after reset 1 the cursor will be zoomed by a factor of 2 in both directions igain 0 expected input level swing is 16 to 235 (8-bit rgb); default after reset 1 expected input level swing is 0 to 255 (8-bit rgb) xint 0 no horizontal interpolation ?lter; default after reset 1 interpolation ?lter for horizontal upscaling is active data byte description yfil1 yfil0 0 0 no ?lter active; default after reset 0 1 ?lter is inserted before vertical scaling 1 0 ?lter is inserted after vertical scaling; yskip should be logic 0 1 1 reserved data byte description gy4 to gy0 gain luminance of rgb (c r , y and c b ) output, ranging from (1 - 16 32 )to(1+ 15 32 ). suggested nominal value = 0, depending on external application. gcd4 to gcd0 gain colour difference of rgb (c r , y and c b ) output, ranging from (1 - 16 32 )to(1+ 15 32 ). suggested nominal value = 0, depending on external application.
2004 mar 04 33 philips semiconductors product speci?cation digital video encoder SAA7104E; saa7105e table 37 subaddress 3ah table 38 subaddress 54h table 39 subaddresses 55h to 59h data byte logic level description cbenb 0 data from input ports is encoded 1 colour bar with ?xed colours is encoded syntv 0 in slave mode, the encoder is only synchronized at the beginning of an odd ?eld; default after reset 1 in slave mode, the encoder receives a vertical sync signal symp 0 horizontal and vertical trigger is taken from fsvgc or both vsvgc and hsvgc; default after reset 1 horizontal and vertical trigger is decoded out of itu-r bt.656 compatible data at pd port demoff 0 y-c b -c r to rgb dematrix is active; default after reset 1y-c b -c r to rgb dematrix is bypassed csync 0 pin hsm_csync provides a horizontal sync for non-interlaced vga components output (at pixclk) 1 pin hsm_csync provides a composite sync for interlaced components output (at xtal clock) y2c 0 input luminance data is twos complement from pd input port 1 input luminance data is straight binary from pd input port; default after reset uv2c 0 input colour difference data is twos complement from pd input port 1 input colour difference data is straight binary from pd input port; default after reset data byte logic level description vpsen 0 video programming system data insertion is disabled; default after reset 1 video programming system data insertion in line 16 is enabled gpval 0 pin vsm provides a low level if gpen = 1 1 pin vsm provides a high level if gpen = 1 gpen 0 pin vsm provides a vertical sync for a monitor; default after reset 1 pin vsm provides a constant signal according to gpval edge 0 input data is sampled with inverse clock edges 1 input data is sampled with the clock edges speci?ed in tables 9 to 14; default after reset slot 0 normal assignment of the input data to the clock edge; default after reset 1 correct time misalignment due to inverted assignment of input data to the clock edge data byte description remarks vps5 ?fth byte of video programming system data in line 16; lsb ?rst; all other bytes are not relevant for vps vps11 eleventh byte of video programming system data vps12 twelfth byte of video programming system data vps13 thirteenth byte of video programming system data vps14 fourteenth byte of video programming system data
2004 mar 04 34 philips semiconductors product speci?cation digital video encoder SAA7104E; saa7105e table 40 subaddress 5ah; note 1 note 1. the default after reset is 00h. table 41 subaddresses 5bh and 5dh table 42 subaddresses 5ch and 5eh table 43 subaddress 5dh notes 1. output black level/ire = blckl 2/6.29 + 28.9. 2. output black level/ire = blckl 2/6.18 + 26.5. data byte description value result chps phase of encoded colour subcarrier (including burst) relative to horizontal sync; can be adjusted in steps of 360/256 degrees 6bh pal b/g and data from input ports in master mode 16h pal b/g and data from look-up table 25h ntsc m and data from input ports in master mode 46h ntsc m and data from look-up table data byte description conditions remarks gainu variable gain for c b signal; input representation in accordance with itu-r bt.601 white-to-black = 92.5 ire gainu = - 2.17 nominal to +2.16 nominal gainu = 0 output subcarrier of u contribution = 0 gainu = 118 (76h) output subcarrier of u contribution = nominal white-to-black = 100 ire gainu = - 2.05 nominal to +2.04 nominal gainu = 0 output subcarrier of u contribution = 0 gainu = 125 (7dh) output subcarrier of u contribution = nominal data byte description conditions remarks gainv variable gain for c r signal; input representation in accordance with itu-r bt.601 white-to-black = 92.5 ire gainv = - 1.55 nominal to +1.55 nominal gainv = 0 output subcarrier of v contribution = 0 gainv = 165 (a5h) output subcarrier of v contribution = nominal white-to-black = 100 ire gainv = - 1.46 nominal to +1.46 nominal gainv = 0 output subcarrier of v contribution = 0 gainv = 175 (afh) output subcarrier of v contribution = nominal data byte description conditions remarks blckl variable black level; input representation in accordance with itu-r bt.601 white-to-sync = 140 ire; note 1 recommended value: blckl = 58 (3ah) blckl = 0; note 1 output black level = 29 ire blckl = 63 (3fh); note 1 output black level = 49 ire white-to-sync = 143 ire; note 2 recommended value: blckl = 51 (33h) blckl = 0; note 2 output black level = 27 ire blckl = 63 (3fh); note 2 output black level = 47 ire
2004 mar 04 35 philips semiconductors product speci?cation digital video encoder SAA7104E; saa7105e table 44 subaddress 5eh notes 1. output black level/ire = blnnl 2/6.29 + 25.4. 2. output black level/ire = blnnl 2/6.18 + 25.9; default after reset: 35h. table 45 subaddress 5fh table 46 logic levels and function of ccrs data byte description conditions remarks blnnl variable blanking level white-to-sync = 140 ire; note 1 recommended value: blnnl = 46 (2eh) blnnl = 0; note 1 output blanking level = 25 ire blnnl = 63 (3fh); note 1 output blanking level = 45 ire white-to-sync = 143 ire; note 2 recommended value: blnnl = 53 (35h) blnnl = 0; note 2 output blanking level = 26 ire blnnl = 63 (3fh); note 2 output blanking level = 46 ire data byte description ccrs select cross-colour reduction ?lter in luminance; see table 46 blnvb variable blanking level during vertical blanking interval is typically identical to value of blnnl ccrs1 ccrs0 description 0 0 no cross-colour reduction; for overall transfer characteristic of luminance see fig.6 0 1 cross-colour reduction #1 active; for overall transfer characteristic see fig.6 1 0 cross-colour reduction #2 active; for overall transfer characteristic see fig.6 1 1 cross-colour reduction #3 active; for overall transfer characteristic see fig.6
2004 mar 04 36 philips semiconductors product speci?cation digital video encoder SAA7104E; saa7105e table 47 subaddress 61h table 48 subaddress 62h data byte logic level description downd 0 digital core in normal operational mode; default after reset 1 digital core in sleep mode and is reactivated with an i 2 c-bus address downa 0 dacs in normal operational mode; default after reset 1 dacs in power-down mode inpi 0 pal switch phase is nominal; default after reset 1 pal switch is inverted compared to nominal if rtce = 1 ygs 0 luminance gain for white - black 100 ire 1 luminance gain for white - black 92.5 ire including 7.5 ire set-up of black scbw 0 enlarged bandwidth for chrominance encoding (for overall transfer characteristic of chrominance in baseband representation see figs 4 and 5) 1 standard bandwidth for chrominance encoding (for overall transfer characteristic of chrominance in baseband representation see figs 4 and 5); default after reset pal 0 ntsc encoding (non-alternating v component) 1 pal encoding (alternating v component) fise 0 864 total pixel clocks per line 1 858 total pixel clocks per line data byte logic level description conditions remarks rtce 0 no real-time control of generated subcarrier frequency; default after reset 1 real-time control of generated subcarrier frequency through a philips video decoder; for a speci?cation of the rtc protocol see document rtc functional description , available on request bsta - amplitude of colour burst; input representation in accordance with itu-r bt.601 white-to-black = 92.5 ire; burst = 40 ire; ntsc encoding recommended value: bsta = 63 (3fh) bsta = 0 to 2.02 nominal white-to-black = 92.5 ire; burst = 40 ire; pal encoding recommended value: bsta = 45 (2dh) bsta = 0 to 2.82 nominal white-to-black = 100 ire; burst = 43 ire; ntsc encoding recommended value: bsta = 67 (43h) bsta = 0 to 1.90 nominal white-to-black = 100 ire; burst = 43 ire; pal encoding recommended value: bsta = 47 (2fh); default after reset bsta = 0 to 3.02 nominal
2004 mar 04 37 philips semiconductors product speci?cation digital video encoder SAA7104E; saa7105e table 49 subaddresses 63h to 66h (four bytes to program subcarrier frequency) note 1. examples: a) ntsc m: f fsc = 227.5, f llc = 1716 ? fsc = 569408543 (21f07c1fh). b) pal b/g: f fsc = 283.7516, f llc = 1728 ? fsc = 705268427 (2a098acbh). table 50 subaddresses 67h to 6ah table 51 subaddresses 6ch and 6dh table 52 subaddress 6dh table 53 subaddress 6eh data byte description conditions remarks fsc0 to fsc3 f fsc = subcarrier frequency (in multiples of line frequency); f llc = clock frequency (in multiples of line frequency) ; note 1 fsc3 = most signi?cant byte; fsc0 = least signi?cant byte data byte description remarks l21o0 ?rst byte of captioning data, odd ?eld lsbs of the respective bytes are encoded immediately after run-in and framing code, the msbs of the respective bytes have to carry the parity bit, in accordance with the de?nition of line 21 encoding format. l21o1 second byte of captioning data, odd ?eld l21e0 ?rst byte of extended data, even ?eld l21e1 second byte of extended data, even ?eld data byte description htrig sets the horizontal trigger phase related to chip-internal horizontal input values above 1715 (fise = 1) or 1727 (fise = 0) are not allowed; increasing htrig decreases delays of all internally generated timing signals; the default value is 0 data byte description vtrig sets the vertical trigger phase related to chip-internal vertical input increasing vtrig decreases delays of all internally generated timing signals, measured in half lines; variation range of vtrig = 0 to 31 (1fh); the default value is 0 data byte logic level description nvtrig 0 values of the vtrig register are positive 1 values of the vtrig register are negative blckon 0 encoder in normal operation mode; default after reset 1 output signal is forced to blanking level phres - selects the phase reset mode of the colour subcarrier generator; see table 54 ldel - selects the delay on luminance path with reference to chrominance path; see table 55 flc - ?eld length control; see table 56 fsc round f fsc f llc ------- - 2 32 ? ?? =
2004 mar 04 38 philips semiconductors product speci?cation digital video encoder SAA7104E; saa7105e table 54 logic levels and function of phres table 55 logic levels and function of ldel table 56 logic levels and function of flc table 57 subaddress 6fh table 58 logic levels and function of ccen data byte description phres1 phres0 0 0 no subcarrier reset 0 1 subcarrier reset every two lines 1 0 subcarrier reset every eight ?elds 1 1 subcarrier reset every four ?elds data byte description ldel1 ldel0 0 0 no luminance delay; default after reset 0 1 1 llc luminance delay 1 0 2 llc luminance delay 1 1 3 llc luminance delay data byte description flc1 flc0 0 0 interlaced 312.5 lines/?eld at 50 hz, 262.5 lines/?eld at 60 hz; default after reset 0 1 non-interlaced 312 lines/?eld at 50 hz, 262 lines/?eld at 60 hz 1 0 non-interlaced 313 lines/?eld at 50 hz, 263 lines/?eld at 60 hz 1 1 non-interlaced 313 lines/?eld at 50 hz, 263 lines/?eld at 60 hz data byte logic level description ccen - enables individual line 21 encoding; see table 58 ttxen 0 disables teletext insertion; default after reset 1 enables teletext insertion sccln - selects the actual line, where closed caption or extended data are encoded; line = (sccln + 4) for m-systems; line = (sccln + 1) for other systems data byte description ccen1 ccen0 0 0 line 21 encoding off; default after reset 0 1 enables encoding in ?eld 1 (odd) 1 0 enables encoding in ?eld 2 (even) 1 1 enables encoding in both ?elds
2004 mar 04 39 philips semiconductors product speci?cation digital video encoder SAA7104E; saa7105e table 59 subaddresses 70h to 72h table 60 subaddress 73h table 61 subaddress 74h table 62 subaddress 75h table 63 subaddresses 76h, 77h and 7ch data byte description adwhs active display window horizontal start; de?nes the start of the active tv display portion after the border colour values above 1715 (fise = 1) or 1727 (fise = 0) are not allowed adwhe active display window horizontal end; de?nes the end of the active tv display portion before the border colour values above 1715 (fise = 1) or 1727 (fise = 0) are not allowed data byte description remarks ttxhs start of signal ttxrq on pin ttxrq_xclko2 (clk2en = 0); see fig.14 ttxhs = 42h; is default after reset if strapped to pal ttxhs = 54h; is default after reset if strapped to ntsc data byte description remarks ttxhd indicates the delay in clock cycles between rising edge of ttxrq output signal on pin ttxrq_xclko2 (clk2en = 0) and valid data at pin ttx_sres minimum value: ttxhd = 2; is default after reset data byte description csynca advanced composite sync against rgb output from 0 xtal clocks to 31 xtal clocks data byte description remarks ttxovs ?rst line of occurrence of signal ttxrq on pin ttxrq_xclko2 (clk2en = 0) in odd ?eld ttxovs = 05h; is default after reset if strapped to pal ttxovs = 06h; is default after reset if strapped to ntsc line = (ttxovs + 4) for m-systems line = (ttxovs + 1) for other systems ttxove last line of occurrence of signal ttxrq on pin ttxrq_xclko2 (clk2en = 0) in odd ?eld ttxove = 16h; is default after reset if strapped to pal ttxove = 10h; is default after reset if strapped to ntsc line = (ttxove + 3) for m-systems line = ttxove for other systems
2004 mar 04 40 philips semiconductors product speci?cation digital video encoder SAA7104E; saa7105e table 64 subaddresses 78h, 79h and 7ch table 65 subaddresses 7ah to 7ch table 66 subaddress 7ch table 67 subaddresses 7eh and 7fh table 68 subaddresses 81h to 83h data byte description remarks ttxevs ?rst line of occurrence of signal ttxrq on pin ttxrq_xclko2 (clk2en = 0) in even ?eld ttxevs = 04h; is default after reset if strapped to pal ttxevs = 05h; is default after reset if strapped to ntsc line = (ttxevs + 4) for m-systems line = (ttxevs + 1) for other systems ttxeve last line of occurrence of signal ttxrq on pin ttxrq_xclko2 (clk2en = 0) in even ?eld ttxeve = 16h; is default after reset if strapped to pal ttxeve = 10h; is default after reset if strapped to ntsc line = (ttxeve + 3) for m-systems line = ttxeve for other systems data byte description fal ?rst active line = fal + 4 for m-systems and fal + 1 for other systems, measured in lines fal = 0 coincides with the first field synchronization pulse lal last active line = lal + 3 for m-systems and lal for other system, measured in lines lal = 0 coincides with the first field synchronization pulse data byte logic level description ttx60 0 enables nabts (fise = 1) or european ttx (fise = 0); default after reset 1 enables world standard teletext 60 hz (fise = 1) ttxo 0 new teletext protocol selected; at each rising edge of ttxrq a single teletext bit is requested (see fig.14); default after reset 1 old teletext protocol selected; the encoder provides a window of ttxrq going high; the length of the window depends on the chosen teletext standard (see fig.14) data byte description line individual lines in both ?elds (pal counting) can be disabled for insertion of teletext by the respective bits, disabled line = linexx (50 hz ?eld rate) this bit mask is effective only if the lines are enabled by ttxovs/ttxove and ttxevs/ttxeve data byte description pcl de?nes the frequency of the synthesized pixel clock pixclko; ; f xtal = 27 mhz nominal, e.g. 640 480 to ntsc m: pcl = 20f63bh; 640 480 to pal b/g: pcl = 1b5a73h (as by strapping pins) f pixclk pcl 2 24 ----------- f xtal ? ?? 8 =
2004 mar 04 41 philips semiconductors product speci?cation digital video encoder SAA7104E; saa7105e table 69 subaddress 84h table 70 logic levels and function of pcle table 71 logic levels and function of pcli table 72 subaddress 85h table 73 subaddresses 90h and 94h data byte logic level description dclk - set to logic 1 (default after reset is logic 0) pclsy 0 pixel clock generator runs free; default after reset 1 pixel clock generator gets synchronized with the vertical sync ifra 0 input fifo gets reset explicitly at falling edge 1 input fifo gets reset every ?eld; default after reset ifbp 0 input fifo is active 1 input fifo is bypassed; default after reset pcle - controls the divider for the external pixel clock; see table 70 pcli - controls the divider for the internal pixel clock; see table 71 data byte description pcle1 pcle0 0 0 divider ratio for pixclk output is 1 0 1 divider ratio for pixclk output is 2; default after reset 1 0 divider ratio for pixclk output is 4 1 1 divider ratio for pixclk output is 8 data byte description pcli1 pcli0 0 0 divider ratio for internal pixclk is 1 0 1 divider ratio for internal pixclk is 2; default after reset 1 0 divider ratio for internal pixclk is 4 1 1 not allowed data byte logic level description eidiv 0 set to logic 0 if dvo compliant signals are applied; default after reset 1 set to logic 1 if non-dvo compliant signals are applied fili - threshold for fifo internal transfers; nominal value is 8; default after reset data byte description xofs horizontal offset; de?nes the number of pixclks from horizontal sync (hsvgc) output to composite blanking ( cbo) output
2004 mar 04 42 philips semiconductors product speci?cation digital video encoder SAA7104E; saa7105e table 74 subaddresses 91h and 94h table 75 subaddresses 92h and 94h table 76 subaddresses 93h and 94h table 77 subaddresses 95h and 96h table 78 subaddress 96h data byte description xpix pixel in x direction; de?nes half the number of active pixels per input line (identical to the length of cbo pulses) data byte description yofso vertical offset in odd ?eld; de?nes (in the odd ?eld) the number of lines from vsvgc to ?rst line with active cbo; if no lut data is requested, the ?rst active cbo will be output at yofso + 2; usually, yofso = yofse with the exception of extreme vertical downscaling and interlacing data byte description yofse vertical offset in even ?eld; de?nes (in the even ?eld) the number of lines from vsvgc to ?rst line with active cbo; if no lut data is requested, the ?rst active cbo will be output at yofse + 2; usually, yofse = yofso with the exception of extreme vertical downscaling and interlacing data byte description ypix de?nes the number of requested input lines from the feeding device; number of requested lines = ypix + yofse - yofso data byte logic level description efs 0 frame sync signal at pin fsvgc ignored in slave mode 1 frame sync signal at pin fsvgc accepted in slave mode pcbn 0 normal polarity of cbo signal (high during active video) 1 inverted polarity of cbo signal (low during active video) slave 0 the SAA7104E; saa7105e is timing master to the graphics controller 1 the SAA7104E; saa7105e is timing slave to the graphics controller ilc 0 if hardware cursor insertion is active, set low for non-interlaced input signals 1 if hardware cursor insertion is active, set high for interlaced input signals yfil 0 luminance sharpness booster disabled 1 luminance sharpness booster enabled
2004 mar 04 43 philips semiconductors product speci?cation digital video encoder SAA7104E; saa7105e table 79 subaddress 97h table 80 subaddresses 98h and 99h table 81 subaddress 99h data byte logic level description hfs 0 horizontal sync is directly derived from input signal (slave mode) at pin hsvgc 1 horizontal sync is derived from a frame sync signal (slave mode) at pin fsvgc (only if efs is set high) vfs 0 vertical sync (?eld sync) is directly derived from input signal (slave mode) at pin vsvgc 1 vertical sync (?eld sync) is derived from a frame sync signal (slave mode) at pin fsvgc (only if efs is set high) ofs 0 pin fsvgc is switched to input 1 pin fsvgc is switched to active output pfs 0 polarity of signal at pin fsvgc in output mode (master mode) is active high; rising edge of the input signal is used in slave mode 1 polarity of signal at pin fsvgc in output mode (master mode) is active low; falling edge of the input signal is used in slave mode ovs 0 pin vsvgc is switched to input 1 pin vsvgc is switched to active output pvs 0 polarity of signal at pin vsvgc in output mode (master mode) is active high; rising edge of the input signal is used in slave mode 1 polarity of signal at pin vsvgc in output mode (master mode) is active low; falling edge of the input signal is used in slave mode ohs 0 pin hsvgc is switched to input 1 pin hsvgc is switched to active output phs 0 polarity of signal at pin hsvgc in output mode (master mode) is active high; rising edge of the input signal is used in slave mode 1 polarity of signal at pin hsvgc in output mode (master mode) is active low; falling edge of the input signal is used in slave mode data byte description hlen horizontal length; data byte description idel input delay; de?nes the distance in pixclks between the active edge of cbo and the ?rst received valid pixel hlen number of pixclks line ---------------------------------------------------- - 1 C =
2004 mar 04 44 philips semiconductors product speci?cation digital video encoder SAA7104E; saa7105e table 82 subaddresses 9ah and 9ch table 83 subaddresses 9bh and 9ch table 84 subaddresses 9dh and 9fh table 85 subaddresses 9eh and 9fh table 86 subaddresses a0h and a1h table 87 subaddress a1h table 88 subaddresses a2h to a4h data byte description xinc incremental fraction of the horizontal scaling engine; data byte description yinc incremental fraction of the vertical scaling engine; data byte description yiwgto weighting factor for the ?rst line of the odd ?eld; data byte description yiwgte weighting factor for the ?rst line of the even ?eld; data byte description yskip vertical line skip; de?nes the effectiveness of the anti-?icker ?lter; yskip = 0: most effective; yskip = 4095: anti-?icker ?lter switched off data byte logic level description blen 0 no internal blanking for non-interlaced graphics in bypass mode; default after reset 1 forced internal blanking for non-interlaced graphics in bypass mode data byte description bcy, bcu and bcv luminance and colour difference portion of border colour in underscan area xinc number of output pixels line ------------------------------------------------------------- - number of input pixels line ---------------------------------------------------------- -------------------------------------------------------------- 4096 = yinc number of active output lines number of active input lines ---------------------------------------------------------------------------- 4096 = yiwgto yinc 2 ------------- - 2048 + = yiwgte yinc yskip C 2 ------------------------------------- - =
2004 mar 04 45 philips semiconductors product speci?cation digital video encoder SAA7104E; saa7105e table 89 subaddress d0h table 90 layout of the data bytes in the line count array table 91 subaddress d1h table 92 layout of the data bytes in the line type array table 93 subaddress d2h data byte description hlca ram start address for the hd sync line count array; the byte following subaddress d0 points to the ?rst cell to be loaded with the next transmitted byte; succeeding cells are loaded by auto-incrementing until stop condition. each line count array entry consists of 2 bytes; see table 90. the array has 15 entries. hlc hd line counter. the system will repeat the pattern described in hlt hlc times and then start with the next entry in line count array. hlt hd line type pointer. if not 0, the value points into the line type array, index hlt - 1 with the description of the current line. 0 means the entry is not used. byte description 0 hlc7 hlc6 hlc5 hlc4 hlc3 hlc2 hlc1 hlc0 1 hlt3 hlt2 hlt1 hlt0 0 0 hlc9 hlc8 data byte description hlta ram start address for the hd sync line type array; the byte following subaddress d1 points to the ?rst cell to be loaded with the next transmitted byte; succeeding cells are loaded by auto-incrementing until stop condition. each line type array entry consists of 4 bytes; see table 92. the array has 15 entries. hlp hd line type; if not 0, the value points into the line pattern array. the index used is hlp - 1. it consists of value-duration pairs. each entry consists of 8 pointers, used from index 0 to 7. the value 0 means that the entry is not used. byte description 0 0 hlp12 hlp11 hlp10 0 hlp02 hlp01 hlp00 1 0 hlp32 hlp31 hlp30 0 hlp22 hlp21 hlp20 2 0 hlp52 hlp51 hlp50 0 hlp42 hlp41 hlp40 3 0 hlp72 hlp71 hlp70 0 hlp62 hlp61 hlp60 data byte description hlpa ram start address for the hd sync line pattern array; the byte following subaddress d2 points to the ?rst cell to be loaded with the next transmitted byte; succeeding cells are loaded by auto-incrementing until stop condition. each line pattern array entry consists of 4 value-duration pairs occupying 2 bytes; see table 94. the array has 7 entries. hpd hd pattern duration. the value de?nes the time in pixel clocks (hpd + 1) the corresponding value hpv is added to the hd output signal. if 0, this entry will be skipped. hpv hd pattern value pointer. this gives the index in the hd value array containing the level to be inserted into the hd output path. if the msb of hpv is logic 1, the value will only be inserted into the y/green channel of the hd data path, the other channels remain unchanged.
2004 mar 04 46 philips semiconductors product speci?cation digital video encoder SAA7104E; saa7105e table 94 layout of the data bytes in the line pattern array table 95 subaddress d3h table 96 layout of the data bytes in the value array table 97 subaddresses d4h and d5h table 98 subaddresses d6h and d7h table 99 subaddresses d8h and d9h byte description 0 hpd07 hpd06 hpd05 hpd04 hpd03 hpd02 hpd01 hpd00 1 hpv03 hpv02 hpv01 hpv00 0 0 hpd09 hpd08 2 hpd17 hpd16 hpd14 hpd14 hpd13 hpd12 hpd11 hpd10 3 hpv13 hpv12 hpv11 hpv10 0 0 hpd19 hpd18 4 hpd27 hpd26 hpd25 hpd24 hpd23 hpd22 hpd21 hpd20 5 hpv23 hpv22 hpv21 hpv20 0 0 hpd29 hpd28 6 hpd37 hpd36 hpd35 hpd34 hpd33 hpd32 hpd31 hpd30 7 hpv33 hpv32 hpv31 hpv30 0 0 hpd39 hpd38 data byte description hpva ram start address for the hd sync value array; the byte following subaddress d3 points to the ?rst cell to be loaded with the next transmitted byte; succeeding cells are loaded by auto-incrementing until stop condition. each line pattern array entry consists of 2 bytes. the array has 8 entries. hpve hd pattern value entry. the hd path will insert a level of (hpv + 52) 0.66 ire into the data path. the value is signed 8-bits wide; see table 96. hhs hd horizontal sync. if the hd engine is active, this value will be provided at pin hsm_csync; see table 96. hvs hd vertical sync. if the hd engine is active, this value will be provided at pin vsm; see table 96. byte description 0 hpve7 hpve6 hpve5 hpve4 hpve3 hpve2 hpve1 hpve0 1 000000hvshhs data byte description hlct state of the hd line counter after trigger, note that it counts backwards hlcpt state of the hd line type pointer after trigger hlppt state of the hd pattern pointer after trigger data byte description hdct state of the hd duration counter after trigger, note that it counts backwards hept state of the hd event type pointer in the line type array after trigger data byte description htx horizontal trigger phase for the hd sync engine in pixel clocks
2004 mar 04 47 philips semiconductors product speci?cation digital video encoder SAA7104E; saa7105e table 100 subaddresses dah and dbh table 101 subaddress dch table 102 subaddresses f0h to f2h table 103 subaddresses f3h to f5h table 104 subaddresses f6h to f8h table 105 subaddresses f9h and fah table 106 subaddress fah data byte description hty vertical trigger phase for the hd sync engine in input lines data byte logic level description hdsye 0 the hd sync engine is off; default after reset 1 the hd sync engine is active hdtc 0 hd output path processes rgb; default after reset 1 hd output path processes yuv hdgy 0 gain in the hd output path is reduced, insertion of sync pulses is possible; default after reset 1 full level swing at the input causes full level swing at the dacs in hd mode hdip 0 interpolator for the colour difference signal in the hd output path is active; default after reset 1 interpolator for the colour difference signals in the hd output path is off data byte description cc1r, cc1g and cc1b red, green and blue portion of ?rst cursor colour data byte description cc2r, cc2g and cc2b red, green and blue portion of second cursor colour data byte description auxr, auxg and auxb red, green and blue portion of auxiliary cursor colour data byte description xcp horizontal cursor position data byte description xhs horizontal hot spot of cursor
2004 mar 04 48 philips semiconductors product speci?cation digital video encoder SAA7104E; saa7105e table 107 subaddresses fbh and fch table 108 subaddress fch table 109 subaddress fdh table 110 subaddress feh table 111 subaddress ffh in subaddresses 5bh, 5ch, 5dh, 5eh, 62h and d3h all ire values are rounded up. data byte description ycp vertical cursor position data byte description yhs vertical hot spot of cursor data byte logic level description lutoff 0 colour look-up table is active 1 colour look-up table is bypassed cmode 0 cursor mode; input colour will be inverted 1 auxiliary cursor colour will be inserted lutl 0 lut loading via input data stream is inactive 1 colour and cursor luts are loaded via input data stream if 0 input format is 8 + 8 + 8-bit 4 :4:4 non-interlaced rgb or c b -y-c r 1 input format is 5 + 5 + 5-bit 4 :4:4 non-interlaced rgb 2 input format is 5 + 6 + 5-bit 4 :4:4 non-interlaced rgb 3 input format is 8 + 8 + 8-bit 4 :2:2 non-interlaced c b -y-c r 4 input format is 8 + 8 + 8-bit 4 :2:2 interlaced c b -y-c r (itu-r bt.656, 27 mhz clock) (in subaddresses 91h and 94h set xpix = number of active pixels/line) 5 input format is 8-bit non-interlaced index colour 6 input format is 8 + 8 + 8-bit 4 :4:4 non-interlaced rgb or c b -y-c r (special bit ordering) matoff 0 rgb to c r -y-c b matrix is active 1 rgb to c r -y-c b matrix is bypassed dfoff 0 down formatter ( 4:4:4to4:2:2) in input path is active 1 down formatter is bypassed data byte description cursa ram start address for cursor bit map; the byte following subaddress feh points to the ?rst cell to be loaded with the next transmitted byte; succeeding cells are loaded by auto-incrementing until stop condition data byte description colsa ram start address for colour lut; the byte following subaddress ffh points to the ?rst cell to be loaded with the next transmitted byte; succeeding cells are loaded by auto-incrementing until stop condition
2004 mar 04 49 philips semiconductors product speci?cation digital video encoder SAA7104E; saa7105e 7.25 slave transmitter table 112 slave transmitter (slave address 89h) table 113 subaddress 00h table 114 subaddress 1ch table 115 subaddress 80h register function subaddress data byte d7 d6 d5 d4 d3 d2 d1 d0 status byte 00h ver2 ver1 ver0 ccrdo ccrde 0 fseq o_e chip id 1ch cid7 cid6 cid5 cid4 cid3 cid2 cid1 cid0 fifo status 80h 0 0 0 0 0 0 ovfl udfl data byte logic level description ver - version identi?cation of the device: it will be changed with all versions of the ic that have different programming models; current version is 101 binary ccrdo 1 closed caption bytes of the odd ?eld have been encoded 0 the bit is reset after information has been written to the subaddresses 67h and 68h; it is set immediately after the data has been encoded ccrde 1 closed caption bytes of the even ?eld have been encoded 0 the bit is reset after information has been written to the subaddresses 69h and 6ah; it is set immediately after the data has been encoded fseq 1 during ?rst ?eld of a sequence (repetition rate: ntsc = 4 ?elds, pal = 8 ?elds) 0 not ?rst ?eld of a sequence o_e 1 during even ?eld 0 during odd ?eld data byte description cid chip id of SAA7104E = 04h; chip id of saa7105e = 05h data byte logic level description iferr 0 normal fifo state 1 input fifo over?ow/under?ow has occurred bferr 0 normal fifo state 1 buffer fifo over?ow, only if yupsc = 1 ovfl 0 no fifo over?ow 1 fifo over?ow has occurred; this bit is reset after this subaddress has been read udfl 0 no fifo under?ow 1 fifo under?ow has occurred; this bit is reset after this subaddress has been read
2004 mar 04 50 philips semiconductors product speci?cation digital video encoder SAA7104E; saa7105e handbook, full pagewidth 6 8 10 12 14 6 0 024 mbe737 - 6 - 12 - 18 - 30 - 24 - 36 - 42 - 54 - 48 f (mhz) g v (db) (1) (2) fig.4 chrominance transfer characteristic 1. (1) scbw = 1. (2) scbw = 0. handbook, halfpage 0 0.4 0.8 1.6 2 0 - 4 - 6 - 2 mbe735 1.2 f (mhz) g v (db) (1) (2) fig.5 chrominance transfer characteristic 2. (1) scbw = 1. (2) scbw = 0.
2004 mar 04 51 philips semiconductors product speci?cation digital video encoder SAA7104E; saa7105e handbook, full pagewidth 6 (1) (2) (4) (3) 8101214 6 0 024 mgd672 - 6 - 12 - 18 - 30 - 24 - 36 - 42 - 54 - 48 f (mhz) g v (db) fig.6 luminance transfer characteristic 1 (excluding scaler). (1) ccrs1 = 0; ccrs0 = 1. (2) ccrs1 = 1; ccrs0 = 0. (3) ccrs1 = 1; ccrs0 = 1. (4) ccrs1 = 0; ccrs0 = 0. handbook, halfpage 02 (1) 6 1 0 - 1 - 2 - 3 - 4 - 5 mbe736 4 f (mhz) g v (db) fig.7 luminance transfer characteristic 2 (excluding scaler). (1) ccrs1 = 0; ccrs0 = 0
2004 mar 04 52 philips semiconductors product speci?cation digital video encoder SAA7104E; saa7105e handbook, full pagewidth 6 8 10 12 14 6 0 024 mgb708 - 6 - 12 - 18 - 30 - 24 - 36 - 42 - 54 - 48 f (mhz) g v (db) fig.8 luminance transfer characteristic in rgb (excluding scaler). handbook, full pagewidth 6 8 10 12 14 6 0 024 mgb706 - 6 - 12 - 18 - 30 - 24 - 36 - 42 - 54 - 48 f (mhz) g v (db) fig.9 colour difference transfer characteristic in rgb (excluding scaler).
2004 mar 04 53 philips semiconductors product speci?cation digital video encoder SAA7104E; saa7105e 8 boundary scan test the SAA7104E; saa7105e has built-in logic and 5 dedicated pins to support boundary scan testing which allows board testing without special hardware (nails). the SAA7104E; saa7105e follows the ieee std. 1149.1 - standard test access port and boundary-scan architecture set by the joint test action group (jtag) chaired by philips. the 5 special pins are test mode select (tms), test clock (tck), test reset ( trst), test data input (tdi) and test data output (tdo). the boundary scan test (bst) functions bypass, extest, intest, sample, clamp and idcode are all supported; see table 116. details about the jtag bst-test can be found in the specification ieee std. 1149.1 . a file containing the detailed boundary scan description language (bsdl) of the SAA7104E; saa7105e is available on request. table 116 bst instructions supported by the SAA7104E; saa7105e instruction description bypass this mandatory instruction provides a minimum length serial path (1 bit) between tdi and tdo when no test operation of the component is required. extest this mandatory instruction allows testing of off-chip circuitry and board level interconnections. sample this mandatory instruction can be used to take a sample of the inputs during normal operation of the component. it can also be used to preload data values into the latched outputs of the boundary scan register. clamp this optional instruction is useful for testing when not all ics have bst. this instruction addresses the bypass register while the boundary scan register is in external test mode. idcode this optional instruction will provide information on the components manufacturer, part number and version number. intest this optional instruction allows testing of the internal logic (no support for customer available). user1 this private instruction allows testing by the manufacturer (no support for customer available). 8.1 initialization of boundary scan circuit the test access port (tap) controller of an ic should be in the reset state (test_logic_reset) when the ic is in functional mode. this reset state also forces the instruction register into a functional instruction such as idcode or bypass. to solve the power-up reset, the standard specifies that the tap controller will be forced asynchronously to the test_logic_reset state by setting the trst pin low. 8.2 device identi?cation codes a device identification register is specified in ieee std. 1149.1b-1994 . it is a 32-bit register which contains fields for the specification of the ic manufacturer, the ic part number and the ic version number. its biggest advantage is the possibility to check for the correct ics mounted after production and to determine the version number of the ics during field service. when the idcode instruction is loaded into the bst instruction register, the identification register will be connected between tdi and tdo of the ic. the identification register will load a component specific code during the capture_data_register state of the tap controller, this code can subsequently be shifted out. at board level this code can be used to verify component manufacturer, type and version number. the device identification register contains 32 bits, numbered 31 to 0, where bit 31 is the most significant bit (nearest to tdi) and bit 0 is the least significant bit (nearest to tdo); see fig.10.
2004 mar 04 54 philips semiconductors product speci?cation digital video encoder SAA7104E; saa7105e handbook, full pagewidth 00000010101 0111000100000100 0101 4-bit version code 16-bit part number 11-bit manufacturer identification tdi tdo 31 msb lsb 28 27 12 11 1 0 1 mhc568 handbook, full pagewidth 00000010101 0111000100000101 0101 4-bit version code 16-bit part number 11-bit manufacturer identification tdi tdo 31 msb lsb 28 27 12 11 1 0 1 mhc569 fig.10 32 bits of identification code. b. saa7105e. a. SAA7104E. 9 limiting values in accordance with the absolute maximum rating system (iec 60134); all ground pins connected together and grounded (0 v); all supply pins connected together. notes 1. condition for maximum voltage at digital inputs or i/o pins: 3.0 v < v ddd < 3.6 v. 2. class 2 according to eia/jesd22-114-b. 3. class b according to eia/jesd22-115-a. symbol parameter conditions min. max. unit v ddd digital supply voltage - 0.5 +4.6 v v dda analog supply voltage - 0.5 +4.6 v v i(a) input voltage at analog inputs - 0.5 +4.6 v v i(n) input voltage at pins xtali, sda and scl - 0.5 v ddd + 0.5 v v i(d) input voltage at digital inputs or i/o pins outputs in 3-state - 0.5 +4.6 v outputs in 3-state; note 1 - 0.5 +5.5 v d v ss voltage difference between v ssa(n) and v ssd(n) - 100 mv t stg storage temperature - 65 +150 c t amb ambient temperature 0 70 c v esd electrostatic discharge voltage human body model; note 2 - 2000 v machine model; note 3 - 200 v
2004 mar 04 55 philips semiconductors product speci?cation digital video encoder SAA7104E; saa7105e 10 thermal characteristics note 1. the overall r th(j-a) value can vary depending on the board layout. to minimize the effective r th(j-a) all power and ground pins must be connected to the power and ground layers directly. an ample copper area direct under the SAA7104E; saa7105e with a number of through-hole plating, which connect to the ground layer (four-layer board: second layer), can also reduce the effective r th(j-a) . please do not use any solder-stop varnish under the chip. in addition the usage of soldering glue with a high thermal conductance after curing is recommended. 11 characteristics t amb = 0 to 70 c (typical values excluded); unless otherwise speci?ed. symbol parameter conditions value unit r th(j-a) thermal resistance from junction to ambient in free air 38 (1) k/w symbol parameter conditions min. typ. max. unit supplies v dda analog supply voltage 3.15 3.3 3.45 v v ddd2 , v ddd3 , v ddd4 digital supply voltage 3.15 3.3 3.45 v v ddd1 digital supply voltage (dvo) 1.045 1.1 1.155 v 1.425 1.5 1.575 v 1.71 1.8 1.89 v 2.375 2.5 2.625 v 3.135 3.3 3.465 v i dda analog supply current note 1 1 110 115 ma i ddd digital supply current note 2 1 175 200 ma inputs v il low-level input voltage v ddd1 = 1.1 v, 1.5 v, 1.8 v or 2.5 v; note 3 - 0.1 - +0.2 v v ddd1 = 3.3 v; note 3 - 0.5 - +0.8 v pins reset, tms, tck, trst and tdi - 0.5 - +0.8 v v ih high-level input voltage v ddd1 = 1.1 v, 1.5 v, 1.8 v or 2.5 v; note 3 v ddd1 - 0.2 - v ddd1 + 0.1 v v ddd1 = 3.3 v; note 3 2 - v ddd1 + 0.3 v pins reset, tms, tck, trst and tdi 2 - v ddd2 + 0.3 v i li input leakage current -- 10 m a c i input capacitance clocks -- 10 pf data -- 10 pf i/os at high-impedance -- 10 pf
2004 mar 04 56 philips semiconductors product speci?cation digital video encoder SAA7104E; saa7105e outputs v ol low-level output voltage v ddd1 = 1.1 v, 1.5 v, 1.8 v or 2.5 v; note 3 0 - 0.1 v v ddd1 = 3.3 v; note 3 0 - 0.4 v pins tdo, ttxrq_xclko2, vsm and hsm_csync 0 - 0.4 v v oh high-level output voltage v ddd1 = 1.1 v, 1.5 v, 1.8 v or 2.5 v; note 3 v ddd1 - 0.1 - v ddd1 v v ddd1 = 3.3 v; note 3 2.4 - v ddd1 v pins tdo, ttxrq_xclko2, vsm and hsm_csync 2.4 - v ddd2 v i 2 c-bus; pins sda and scl v il low-level input voltage - 0.5 - 0.3v ddd2 v v ih high-level input voltage 0.7v ddd2 - v ddd2 + 0.3 v i i input current v i = low or high - 10 - +10 m a v ol low-level output voltage (pin sda) i ol =3ma -- 0.4 v i o output current during acknowledge 3 -- ma clock timing; pins pixclki and pixclko t pixclk cycle time note 4 12 -- ns t d(clkd) delay from pixclko to pixclki note 5 --- ns d duty factor t high /t pixclk note 4 40 50 60 % duty factor t high /t clko2 output 40 50 60 % t r rise time note 4 -- 1.5 ns t f fall time note 4 -- 1.5 ns input timing t su;dat input data set-up time pins pd11 to pd0 2 -- ns t hd;dat input data hold time pins pd11 to pd0 0.9 -- ns t su;dat input data set-up time pins hsvgc, vsvgc and fsvgc; note 6 2 -- ns t hd;dat input data hold time pins hsvgc, vsvgc and fsvgc; note 6 1.5 -- ns crystal oscillator f nom nominal frequency - 27 - mhz d f/f nom permissible deviation of nominal frequency note 7 - 50 - +50 10 - 6 symbol parameter conditions min. typ. max. unit
2004 mar 04 57 philips semiconductors product speci?cation digital video encoder SAA7104E; saa7105e c rystal specification t amb ambient temperature 0 - 70 c c l load capacitance 8 -- pf r s series resistance -- 80 w c 1 motional capacitance (typical) 1.2 1.5 1.8 ff c 0 parallel capacitance (typical) 2.8 3.5 4.2 pf data and reference signal output timing c o(l) output load capacitance 8 - 40 pf t o(h)(gfx) output hold time to graphics controller pins hsvgc, vsvgc, fsvgc and cbo 1.5 -- ns t o(d)(gfx) output delay time to graphics controller pins hsvgc, vsvgc, fsvgc and cbo -- 10 ns t o(h) output hold time pins tdo, ttxrq_xclko2, vsm and hsm_csync 3 -- ns t o(d) output delay time pins tdo, ttxrq_xclko2, vsm and hsm_csync -- 25 ns cvbs and rgb outputs v o(cvbs)(p-p) output voltage cvbs (peak-to-peak value) see table 117 - 1.23 - v v o(vbs)(p-p) output voltage vbs (s-video) (peak-to-peak value) see table 117 - 1 - v v o(c)(p-p) output voltage c (s-video) (peak-to-peak value) see table 117 - 0.89 - v v o(rgb)(p-p) output voltage r, g, b (peak-to-peak value) see table 117 - 0.7 - v d v o inequality of output signal voltages - 2 - % r o(l) output load resistance - 37.5 -w b dac output signal bandwidth of dacs - 3 db; note 8 - 170 - mhz ile lf(dac) low frequency integral linearity error of dacs -- 3 lsb dle lf(dac) low frequency differential linearity error of dacs -- 1 lsb symbol parameter conditions min. typ. max. unit
2004 mar 04 58 philips semiconductors product speci?cation digital video encoder SAA7104E; saa7105e notes 1. minimum value for i 2 c-bus bit downa = 1. 2. minimum value for i 2 c-bus bit downd = 1. 3. levels refer to pins pd11 to pd0, fsvgc, pixclki, vsvgc, pixclko, cbo, tvd, and hsvgc, being inputs or outputs directly connected to a graphics controller. input sensitivity is 1 / 2 v ddd2 + 100 mv for high and 1 / 2 v ddd2 - 100 mv for low. the reference voltage 1 / 2 v ddd2 is generated on chip. 4. the data is for both input and output direction. 5. this parameter is arbitrary, if pixclki is looped through the vgc. 6. tested with programming ifbp = 1. 7. if an internal oscillator is used, crystal deviation of nominal frequency is directly proportional to the deviation of subcarrier frequency and line/field frequency. 8. with r l = 37.5 w and c ext = 20 pf (typical). b 3db C 1 2 p r l c ext 5 pf + () ------------------------------------------------ = handbook, full pagewidth pixclko pixclki pdn any output t d(clkd) t high t f t r v oh 0.5v ddd1 v ol t hd;dat t hd;dat t o(h) t o(d) t su;dat t su;dat t pixclk v ih 0.5v ddd1 v il v oh v ol v ih v il mhc567 fig.11 input/output timing specification.
2004 mar 04 59 philips semiconductors product speci?cation digital video encoder SAA7104E; saa7105e handbook, full pagewidth hsvgc pd cbo xofs idel xpix hlen mhb905 fig.12 horizontal input timing. handbook, full pagewidth hsvgc vsvgc cbo yofs ypix mhb906 fig.13 vertical input timing.
2004 mar 04 60 philips semiconductors product speci?cation digital video encoder SAA7104E; saa7105e 11.1 teletext timing time t fd is the time needed to interpolate input data ttx and insert it into the cvbs and vbs output signal, such that it appears at t ttx = 9.78 m s (pal) or t ttx = 10.5 m s (ntsc) after the leading edge of the horizontal synchronization pulse. time t pd is the pipeline delay time introduced by the source that is gated by ttxrq_xclko2 in order to deliver ttx data. this delay is programmable by register ttxhd. for every active high state at output pin ttxrq_xclko2, a new teletext bit must be provided by the source. since the beginning of the pulses representing the ttxrq signal and the delay between the rising edge of ttxrq and valid teletext input data are fully programmable (ttxhs and ttxhd), the ttx data is always inserted at the correct position after the leading edge of the outgoing horizontal synchronization pulse. time t i(ttxw) is the internally used insertion window for ttx data; it has a constant length that allows insertion of 360 teletext bits at a text data rate of 6.9375 mbits/s (pal), 296 teletext bits at a text data rate of 5.7272 mbits/s (world standard ttx) or 288 teletext bits at a text data rate of 5.7272 mbits/s (nabts). the insertion window is not opened if the control bit ttxen is zero. using appropriate programming, all suitable lines of the odd field (ttxovs and ttxove) plus all suitable lines of the even field (ttxevs and ttxeve) can be used for teletext insertion. it is essential to note that the two pins used for teletext insertion must be configured for this purpose by the correct i 2 c-bus register settings . handbook, full pagewidth t i(ttxw) t ttx t pd t fd cvbs/y ttx_sres ttxrq_xclko2 text bit #: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 mhb891 fig.14 teletext timing.
2004 mar 04 61 philips semiconductors product speci?cation digital video encoder SAA7104E; saa7105e 12 application information handbook, full pagewidth mhc574 fltr0 dgnd agnd dvo supply + 3.3 v digital supply + 3.3 v analog supply dgnd 10 pf 27 mhz 0.1 m h 0.1 m f 0.1 m f 0.1 m f 1 nf 10 pf agnd v ddd2 to v ddd4 v ssd1 to v ssd4 v ssa rset dump v dda1 to v dda3 green_vbs_cvbs use one capacitor for each v ddd use one capacitor for each v dda v ddd1 digital inputs and outputs xtali xtalo agnd agnd agnd dgnd agnd 75 w 75 w agnd agnd u y fltr1 red_cr_c_cvbs agnd 75 w 1 k w 12 w 75 w agnd agnd u c fltr2 blue_cb_cvbs vsm, hsm_csync agnd 75 w 75 w agnd agnd u cvbs SAA7104E saa7105e fig.15 application circuit.
2004 mar 04 62 philips semiconductors product speci?cation digital video encoder SAA7104E; saa7105e handbook, halfpage mhb912 2.7 m h 120 pf c16 jp11 jp12 fin fout c10 390 pf c13 560 pf l2 2.7 m h l3 filter 1 = byp. ll act. agnd fig.16 fltr0, fltr1 and fltr2 of fig.15.
2004 mar 04 63 philips semiconductors product speci?cation digital video encoder SAA7104E; saa7105e handbook, full pagewidth 39 pf 39 pf 27.00 mhz 18 pf 1 nf 4.7 m h 18 pf 27.00 mhz SAA7104E saa7105e SAA7104E saa7105e a5 xtali xtalo a6 a5 xtali xtalo a6 mhc570 handbook, full pagewidth r s n.c. clock 27.00 mhz SAA7104E saa7105e SAA7104E saa7105e a5 xtali xtalo a6 a5 xtali xtalo a6 mhc571 fig.17 oscillator application. (1a) with 3rd-harmonic quartz. crystal load = 8 pf. (1b) with fundamental quartz. crystal load = 20 pf. (2a) with direct clock. (2b) with fundamental quartz and restricted drive level. when p drive of the internal oscillator is too high, a resistance r s can be placed in series with the oscillator output xtalo. note: the decreased crystal amplitude results in a lower drive level but on the other hand the jitter performance will decrease.
2004 mar 04 64 philips semiconductors product speci?cation digital video encoder SAA7104E; saa7105e 12.1 reconstruction ?lter figure 16 shows a possible reconstruction filter for the digital-to-analog converters. due to its cut-off frequency of ~ 6 mhz, it is not suitable for hdtv applications. 12.2 analog output voltages the analog output voltages are dependent on the total load (typical value 37.5 w ), the digital gain parameters and the i 2 c-bus settings of the dac reference currents (analog settings). the digital output signals in front of the dacs under nominal (nominal here stands for the settings given in tables 41 to 48 for example a standard pal or ntsc signal) conditions occupy different conversion ranges, as indicated in table 117 for a 100 100 colour bar signal. by setting the reference currents of the dacs as shown in table 117, standard compliant amplitudes can be achieved for all signal combinations; it is assumed that in subaddress 16h, parameter dacf = 0000b, that means the fine adjustment for all dacs in common is set to 0%. if s-video output is desired, the adjustment for the c (chrominance subcarrier) output should be identical to the one for vbs (luminance plus sync) output. table 117 digital output signals conversion range set/out cvbs, sync tip-to-white vbs, sync tip-to-white rgb, black-to-white digital settings see tables 41 to 48 see tables 41 to 48 see table 36 digital output 1014 881 876 analog settings e.g. b dac = 1fh e.g. g dac = 1bh e.g. r dac = g dac = b dac = 0bh analog output 1.23 v (p-p) 1.00 v (p-p) 0.70 v (p-p) 12.3 suggestions for a board layout use separate ground planes for analog and digital ground. connect these planes only at one point directly under the device, by using a 0 w resistor directly at the supply stage. use separate supply lines for analog and digital supply. place the supply decoupling capacitors close to the supply pins. use l bead (ferrite coil) in each digital supply line close to the decoupling capacitors to minimize radiation energy (emc). place the analog coupling (clamp) capacitors close to the analog input pins. place the analog termination resistors close to the coupling capacitors. be careful of hidden layout capacitors around the crystal application. use serial resistors in clock, sync and data lines, to avoid clock or data reflection effects and to soften data energy.
2004 mar 04 65 philips semiconductors product speci?cation digital video encoder SAA7104E; saa7105e 13 package outline 1 a a 1 e 1 b a 2 a 1 a 2 detail x y unit d y e references outline version european projection issue date 00-03-04 03-01-22 iec jedec jeita mm 0.5 0.3 1.75 15.2 14.8 d 1 13.7 13.0 13.7 13.0 e 1 13 e 2 13 1.25 1.05 y 1 0.6 0.4 0.1 0.15 0.35 dimensions (mm are the original dimensions) sot472-1 144e ms-034 - - - 15.2 14.8 ew 0.3 v 05 10 mm scale sot472-1 bga156: plastic ball grid array package; 156 balls; body 15 x 15 x 1.15 mm a max. y 1 c c e 1 d d 1 x e 1 a b c d e f g h j k l m n p 234567891011121314 b a ball a1 index area e e e 1 b e 2 a c c b ? v m ? w m shape optional (4x) 1/2 e 1/2 e
2004 mar 04 66 philips semiconductors product speci?cation digital video encoder SAA7104E; saa7105e 14 soldering 14.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for fine pitch smds. in these situations reflow soldering is recommended. 14.2 re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 270 c depending on solder paste material. the top-surface temperature of the packages should preferably be kept: below 225 c (snpb process) or below 245 c (pb-free process) C for all bga, htsson-t and ssop-t packages C for packages with a thickness 3 2.5 mm C for packages with a thickness < 2.5 mm and a volume 3 350 mm 3 so called thick/large packages. below 240 c (snpb process) or below 260 c (pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm 3 so called small/thin packages. moisture sensitivity precautions, as indicated on packing, must be respected at all times. 14.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 c or 265 c, depending on solder material applied, snpb or pb-free respectively. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 14.4 manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
2004 mar 04 67 philips semiconductors product speci?cation digital video encoder SAA7104E; saa7105e 14.5 suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your philips semiconductors sales office. 2. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 3. these transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 c 10 c measured in the atmosphere of the reflow oven. the package body peak temperature must be kept as low as possible. 4. these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 5. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 6. wave soldering is suitable for lqfp, tqfp and qfp packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 7. wave soldering is suitable for ssop, tssop, vso and vssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 8. image sensor packages in principle should not be soldered. they are mounted in sockets or delivered pre-mounted on flex foil. however, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. the appropriate soldering profile can be provided on request. 9. hot bar or manual soldering is suitable for pmfp packages. package (1) soldering method wave reflow (2) bga, htsson..t (3) , lbga, lfbga, sqfp, ssop..t (3) , tfbga, uson, vfbga not suitable suitable dhvqfn, hbcc, hbga, hlqfp, hso, hsop, hsqfp, hsson, htqfp, htssop, hvqfn, hvson, sms not suitable (4) suitable plcc (5) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (5)(6) suitable ssop, tssop, vso, vssop not recommended (7) suitable cwqccn..l (8) , pmfp (9) , wqccn..l (8) not suitable not suitable
2004 mar 04 68 philips semiconductors product speci?cation digital video encoder SAA7104E; saa7105e 15 data sheet status notes 1. please consult the most recently issued data sheet before initiating or completing a design. 2. the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the latest information is available on the internet at url http://www.semiconductors.philips.com. 3. for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. level data sheet status (1) product status (2)(3) definition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn). 16 definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 17 disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2004 mar 04 69 philips semiconductors product speci?cation digital video encoder SAA7104E; saa7105e 18 purchase of philips i 2 c components purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
? koninklijke philips electronics n.v. 2004 sca76 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. philips semiconductors C a worldwide company contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales of?ces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . printed in the netherlands r21/01/pp 70 date of release: 2004 mar 04 document order number: 9397 750 11436

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